Low-pin-count non-volatile memory embedded in a integrated circuit without any additional pins for access

An electronic system, comprising:

• a processor;
• and
• at least one low-pin-count non-volatile memory (NVM) operatively connected to the processor, the NVM includes at least one or more NVM cells for trimming, at least one of the NVM cells comprising:
• an NVM element coupled to a first supply voltage line;
• a selector coupled to the NVM element and a second supply voltage line having a select signal;
• at least one test mode detection circuit to detect out of normal operational conditions to activate a test mode;
• and
• wherein at least one I/O pins or supply voltages in the integrated circuit can be used to generate at least one select signal to select at least one of the NVM cells of the NVM while the test mode is activated.

A method for providing a low-pin-count nonvolatile memory (NVM) in an integrated circuit comprises:

• providing one or more NVM cells, at least one of the NVM cells comprising:
• an NVM element coupled to a first supply voltage line;
• a selector coupled to the NVM element and a second supply voltage line having a select signal;
• detecting abnormal operation conditions of the NVM;
• and
• activating a test mode if the detecting detects the abnormal operation conditions,
• wherein at least one I/O or supply voltages of the integrated circuit can be used as the I/O or supply voltages of the NVM to select at least one of the NVM cells after the test mode is activated.