Multichip power semiconductor device
AssigneeInfineon Technologies AG
InventorsJoachim Mahler, Thomas Bemmerl, Anton Prueckl
Life of this patent
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Abstract
An electronic device includes a first chip carrier and a second chip carrier isolated from the first chip carrier. A first power semiconductor chip is mounted on and electrically connected to the first chip carrier. A second power semiconductor chip is mounted on and electrically connected to the second chip carrier. An electrically insulating material is configured to at least partially surround the first power semiconductor chip and the second power semiconductor chip. An electrical interconnect is configured to electrically connect the first power semiconductor chip to the second power semiconductor chip, wherein the electrical interconnect has at least one of a contact clip and a galvanically deposited conductor.
Claims21
An electronic device, comprising:
- a first chip carrier;
- a second chip carrier isolated from the first chip carrier, wherein the first and second chip carriers each comprise a double layer structure comprising an upper layer and a lower layer connected to the upper layer by vias;
- a first power semiconductor chip mounted on and electrically connected to the upper layer of the double layer structure of the first chip carrier;
- a second power semiconductor chip mounted on and electrically connected to the upper layer of the double layer structure of the second chip carrier;
- an electrically insulating material configured to at least partially surround the first power semiconductor chip and the second power semiconductor chip;
- and
- an electrical interconnect configured to electrically connect a load electrode of the first power semiconductor chip to a load electrode of the second power semiconductor chip.
An electronic device, comprising:
- a first chip carrier;
- a second chip carrier isolated from the first chip carrier, wherein the first and second chip carriers each comprise a double layer structure comprising an upper layer and a lower layer connected to the upper layer by vias;
- a first power semiconductor chip mounted on and electrically connected to the upper layer of the double layer structure of the first chip carrier;
- a second power semiconductor chip mounted on and electrically connected to the upper layer of the double layer structure of the second chip carrier;
- an electrically insulating material configured to at least partially surround the first power semiconductor chip and the second power semiconductor chip;
- and
- an electrical interconnect configured to electrically connect a load electrode of the first power semiconductor chip to a load electrode of the second power semiconductor chip, wherein a first section of the electrical interconnect is mounted on a first contact pad arranged on a top main face of the first power semiconductor chip and a second section of the electrical interconnect is mounted on the second chip carrier, and
- wherein the first section extends in a direction parallel to a plane defined by the first chip carrier or the second chip carrier and the second section extends in a direction perpendicular to the plane defined by the first chip carrier or the second chip carrier.
An electronic device, comprising:
- a first chip carrier;
- a second chip carrier isolated from the first chip carrier, wherein the first and second chip carriers each comprise a double layer structure comprising an upper layer and a lower layer connected to the upper layer by vias, and wherein the upper layer of the first and second chip carriers is displaced in lateral direction relative to the lower layer of the first and second chip carriers, respectively;
- a first power semiconductor chip mounted on and electrically connected to the upper layer of the double layer structure of the first chip carrier;
- a second power semiconductor chip mounted on and electrically connected to the upper layer of the double layer structure of the second chip carrier;
- an electrically insulating material configured to at least partially surround the first power semiconductor chip and the second power semiconductor chip;
- and
- an electrical interconnect configured to electrically connect a load electrode of the first power semiconductor chip to a load electrode of the second power semiconductor chip.
Dependencies are inferred from the claim text.