# US 8,916,394 B2 · Method for manufacturing a carbon nanotube field emission device with overhanging gate

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- Number: US 8,916,394 B2
- Document ID: US8916394B2
- Status: Granted
- Kind: B2
- Application number: 13/919,842
- Filed: 2013-06-17
- Published: 2013-10-24
- Granted: 2014-12-23
- Earliest claimed: 2007-06-18
- Assignees: California Institute of Technology
- Applicants: California Institute of Technology
- Inventors: Risaku Toda; Michael J. Bronikowski; Edward M. Luong; Harish Manohara
- Web page: https://patentgrep.com/patent/US8916394B2

## CPC

- H10P 50/00: Etching of wafers, substrates or parts of devices
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- B82Y 20/00: Nanooptics, e.g. quantum optics or photonic crystals
- H01J 1/3042: {microengineered, e.g. Spindt-type}
- H01J 1/3044: {Point emitters}
- H01J 3/021: {Electron guns using a field emission, photo emission, or secondary emission electron source}
- H01J 3/022: {with microengineered cathode, e.g. Spindt-type}
- H01J 9/025: {of field emission cathodes}
- B82Y 40/00: Manufacture or treatment of nanostructures
- H01J 2203/0224: Arrangement of gate openings
- Y10S 977/842: for carbon nanotubes or fullerenes
- Y10S 977/939: Electron emitter, e.g. spindt emitter tip coated with nanoparticles
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H01J: ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS (spark-gaps H01T; electric arc lamps H05B31/00; particle accelerators H05H)
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A carbon nanotube field emission device with overhanging gate fabricated by a double silicon-on-insulator process. Other embodiments are described and claimed.

## Claims

### Claim 1

A semiconductor process applied to a wafer, the wafer comprising a silicon substrate; a first insulator layer on the silicon substrate; a first silicon layer on the first insulator layer; a second insulator layer on the first silicon layer; and a second silicon layer on the second insulator layer; the semiconductor process comprising:
etching through the second silicon layer, through the second insulator layer, and through the first silicon layer to the first insulator layer to define a hole;
lateral etching in the first silicon layer to laterally enlarge the hole at the first silicon layer;
etching through the first insulator layer to the substrate, so that the hole has a bottom that includes the substrate;
depositing a removable material on the wafer; and
forming an array of carbon nanotubes at the bottom of the hole on the substrate.

### Claim 2 (depends on 1)

The semiconductor process as set forth in claim 1, where the depositing the removable material on the wafer comprises depositing the removable material on the substrate at the bottom of the hole.

### Claim 3 (depends on 2)

The semiconductor process as set forth in claim 2, where forming the array of carbon nanotubes at the bottom of the hole on the substrate further comprises:
patterning the removable material to provide a pattern for a catalyst; depositing the catalyst on the substrate at the bottom of the hole; and growing the array of carbon nanotubes on the catalyst.

### Claim 4 (depends on 3)

The semiconductor process as set forth in claim 3 further comprising removing the removable material from the wafer after depositing the catalyst on the substrate at the bottom of the hole and before growing the array of carbon nanotubes on the catalyst.

### Claim 5 (depends on 1)

The semiconductor process as set forth in claim 1, where depositing the removable material comprises depositing the removable material on the wafer so that the removable material bridges the opening of the hole.

### Claim 6 (depends on 5)

The semiconductor process as set forth in claim 5, where forming the array of carbon nanotubes at the bottom of the hole on the substrate further comprises: patterning the removable material to provide a pattern for a catalyst; depositing the catalyst on the substrate at the bottom of the hole; and growing the array of carbon nanotubes on the catalyst.

### Claim 7 (depends on 6)

The semiconductor process as set forth in claim 6, where patterning the removable material to provide a pattern for a catalyst comprises forming a plurality of openings through which the catalyst for carbon nanotube formation is adapted to be deposited onto the bottom of the hole on the substrate.

### Claim 8 (depends on 6)

The semiconductor process as set forth in claim 6, where the catalyst is comprised within a catalyst dot array.

### Claim 9 (depends on 1)

The semiconductor process as set forth in claim 1, where the removable material is a photoresist material.

### Claim 10 (depends on 1)

The semiconductor process as set forth in claim 1, further comprising depositing a second material on the wafer after removing the removable material from the wafer.

### Claim 11 (depends on 10)

The semiconductor process as set forth in claim 10, where the second material comprises sol-gel material or micro glass-blowing material.

### Claim 12 (depends on 11)

The semiconductor process as set forth in claim 11, where the micro glass-blowing material is a sol-gel or epoxy material.

### Claim 13 (depends on 1)

The semiconductor process as set forth in claim 1, where the first and second insulator layers comprise silicon dioxide.

### Claim 14 (depends on 1)

The semiconductor process as set forth in claim 1, where the second silicon layer forms a gate with respect to at least one carbon nanotubes in the array of carbon nanotubes at the bottom of the hole on the substrate.

### Claim 15 (depends on 1)

The semiconductor process as set forth in claim 1, where the hole has a top and a sidewall, the second silicon layer forming at least a portion of the sidewall wherein the second silicon layer at the top of the hole overhangs the sidewall.