Hardware instructions to accelerate table-driven mathematical computation of reciprocal square, cube, forth root and their reciprocal functions, and the evaluation of exponential and logarithmic families of functions

A computer-implemented method for using hardware instructions to accelerate table-driven evaluation of mathematical functions, comprising:

• providing a table used for generating values of a plurality of mathematical functions;
• executing a first hardware instruction to lookup a first value for use in a first stage of evaluation for a mathematical function, the first value retrieved from the table;
• executing a second hardware instruction to retrieve a second value for use in a second stage of evaluation for the mathematical function, the second value retrieved from the table to be used in conjunction with the first value retrieved by the first hardware instruction;
• and said retrieving of the second value being performed by using the same input as the first hardware instruction, using a value saved by a lookup from a FIFO queue or using a value saved in a slot according to an immediate tag provided to the second hardware instruction;
• executing a third hardware instruction to perform an extended-range fused multiply-add operation, the extended-range fused multiply-add operation performing a range reduction on the mathematical function using the first value;
• wherein the mathematical function is computed with a single iteration of each of the first hardware instruction, second hardware instruction, and the third hardware instruction, and wherein the first floating-point instruction, second floating-point instruction, and the third floating-point instruction are executed in the processor as a branch-free sequence of instructions.