Adaptive workload based optimizations coupled with a heterogeneous current-aware baseline design to mitigate current delivery limitations in integrated circuits

A system for integrated circuit (IC) chip and package design and IC chip operation comprising:

• a computer system including a memory storage device and a programmed processor unit in communication with said memory storage device, said programmed processor unit configured to:
• divide a layout region of said chip containing one or more current sources, one or more electrical connectors and grid networks, into a number of bins, said electrical connectors delivering electrical current drawn by said current sources of said layout region via said grid networks;
• generate a data structure representing a current distribution relation between said bins and the one or more electrical connectors, the data structure comprising a set of weighted vectors, each weighted vector representing a sensitivity of electrical connector currents with respect to each said bin, and indicating for each bin, a portion of bin current distributed to each electrical connector;
• obtain, using said data structure, an amount of current flow via said electrical connectors with respect to an amount of current drawn by said current sources in said bins;
• and
• determine, using said current flow and current drawn amounts, a non-uniform allocation of electrical connectors to IC regions where blocks having said one or more current sources are located, with respect to one or more objectives and constraints, wherein a constraint includes a limit of electrical connector current to be drawn and a block including a central processing unit including one or more cores operating therein in said layout region, and
• subsequently operate blocks in said regions at current draw activity levels according to the non-uniform allocation, wherein to subsequently operate, a programmed processor unit performs
• scheduling workload operations of applications to run at said IC at scheduled times at a region of said layout, said host system allocating said workload operations of said applications to said one or more cores based on the type of instructions of said applications and according to the non-uniform allocation of said electrical connectors.

A computer program product for integrated circuit (IC) chip and IC chip operation, the computer program product comprising a tangible storage device readable by a processing circuit and storing instructions run by the processing circuit for performing a method, the method comprising:

• dividing a layout region of said chip containing one or more current sources, one or more electrical connectors and grid networks, into a number of bins, said electrical connectors delivering electrical current drawn by said current sources of said layout region via said grid networks;
• generating a data structure representing a current distribution relation between said bins and the one or more electrical connectors, the data structure comprising a set of weighted vectors, each weighted vector representing a sensitivity of electrical connector currents with respect to each said bin, and indicating for each bin, a portion of bin current distributed to each electrical connector;
• obtaining, using said data structure, an amount of current flow via said electrical connectors with respect to an amount of current drawn by said current sources in said bins;
• and
• determining, using said current flow and current drawn amounts, a non-uniform allocation of electrical connectors to IC regions where blocks having said one or more current sources are located, with respect to one or more objectives and constraints, wherein a constraint includes a limit of electrical connector current to be drawn and a block including a central processing unit including one or more cores operating therein in said layout region, and
• subsequently operating blocks in said regions at current draw activity levels according to the non-uniform allocation, said operating including:
• scheduling, by an operating system (O/S) or hypervisor or a host system, workload operations of applications to run at said IC at scheduled times at a region of said layout, said host system allocating said workload operations of said applications to said one or more cores based on the type of instructions of said applications and according to the non-uniform allocation of said electrical connectors.