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US 8,914,758 B1Granted
Equivalence checking using structural analysis on data flow graphs
AssigneeSynopsys, Inc.
InventorsSudipta Kundu, Carl Preston Pixley
Life of this patent
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AssigneeSynopsys, Inc.
InventorsSudipta Kundu, Carl Preston Pixley
Estimating the term…
A design is verified by using equivalence checking to compare a word-level description of the design to a bit-level description of the design. A word-level data flow graph (DFG) based on the word-level description and a bit-level DFG is obtained. Structural analysis is used to reduce the graphs and partition them into smaller portions for the equivalence checking. The analysis includes searching the bit-level DFG to find partial-product encoding and removing redundancy from the bit-level DFG. A reference model with architectural information from the bit-level DFG is created based on the word-level DFG. The reference model is reduced and equivalence checked against the bit-level DFG to determine if the word-level description is equivalent to the bit-level description.
A computer-implemented method for verification analysis comprising:
A computer system for verification analysis comprising:
A computer program product embodied in a non-transitory computer readable medium for verification analysis comprising:
Dependencies are inferred from the claim text.