US 8,914,709 B1 · Manufacturing testing for LDPC codes

Abstract

A storage system includes a channel detector, an LDPC decoder, and an erasure block. The channel detector is configured to receive data corresponding to data read from a storage and output an LLR signal. The LDPC decoder is configured to receive the LLR signal and output a feedback signal to the channel detector. The erasure block is configured to erase at a portion of at least one of the LLR signal and the feedback signal. A method for testing includes generating an error rate function corresponding to an erasure pattern. The function is a function of a number of LDPC iterations. The method includes determining testing parameters at least in part based on the error rate function, wherein the testing parameters comprise a testing number of LDPC iterations, a passing error rate, and the erasure pattern. The method includes testing storage devices using the testing parameters.

Claims15

Dependent claims

A system for testing storage devices, comprising:

a processor;
and
a memory coupled with the processor, wherein the memory is configured to provide the processor with instructions which when executed cause the processor to:
generate an error rate function, wherein the error rate function is a function of a number of LDPC iterations, and wherein the error rate function corresponds to an erasure pattern;
determine a set of testing parameters at least in part based on the error rate function, wherein the set of testing parameters comprises a testing number of LDPC iterations, a passing error rate, and the erasure pattern;
and
test one or more storage devices using the set of testing parameters.

4 more elements

Dependencies are inferred from the claim text.

Manufacturing testing for LDPC codes

Life of this patent

Manufacturing testing for LDPC codes

Life of this patent

Abstract

Claims15