Mechanism for achieving high memory reliablity, availability and serviceability
AssigneeIntel Corporation
InventorsDebaleena Das, Kai Cheng, Jonathan C. Jasper
Life of this patent
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Abstract
A mechanism is described for achieving high memory reliability, availability, and serviceability (RAS) according to one embodiment of the invention. A method of embodiments of the invention includes detecting a permanent failure of a first memory device of a plurality of memory devices of a first channel of a memory system at a computing system, and eliminating the first failure by merging a first error-correction code (ECC) locator device of the first channel with a second ECC locator device of a second channel, wherein merging is performed at the second channel.
Claims14
A method comprising:
- tracking errors associated with a plurality of memory devices;
- predictively detecting, based on the tracked errors, a first failure of a first memory device of a plurality of memory devices of a first channel of a memory system at a computing system;
- and
- eliminating the first failure by merging a first error control device of the first channel with a second error control device of a second channel, wherein the merging of the first and second error control devices forms a first buddy line at the second channel, wherein the first buddy line represents an extension of a locator line providing a first locator associated with a first error control device merged with a second locator associated with a second error control device, wherein the first buddy line is further extended into a second buddy line by merging a third locator with the first and second locators if a second failure of the first memory device or a second memory device is predictively detected, wherein each of the first and second error control devices comprises an error-correction code (ECC) device having at least one of a parity and a locator.
An apparatus comprising:
- first logic to track errors associated with a plurality of memory devices, and predictively detect, based on the tracked errors, a first failure of a first memory device of a plurality of memory devices of a first channel of a memory system at a computing system;
- and
- second logic to eliminate the first failure by merging a first error control device of the first channel with a second error control device of a second channel, wherein the merging of the first and second error control devices forms a first buddy line at the second channel, wherein the first buddy line represents an extension of a locator line providing a first locator associated with a first error control device merged with a second locator associated with a second error control device, wherein the first buddy line is further extended into a second buddy line by merging a third locator with the first and second locators if a second failure of the first memory device or a second memory device is predictively detected, wherein each of the first and second error control devices comprises an error-correction code (ECC) device having at least one of a parity and a locator.
At least one non-transitory machine-readable medium having stored thereon instructions which when executed by a processing device, cause the processing device to perform one or more operations comprising:
- tracking errors associated with a plurality of memory devices;
- predictively detecting, based on the tracked errors, a first failure of a first memory device of a plurality of memory devices of a first channel of a memory system at a computing system;
- and
- eliminating the first failure by merging a first error control device of the first channel with a second error control device of a second channel, wherein the merging of the first and second error control devices forms a first buddy line at the second channel, wherein the first buddy line represents an extension of a locator line providing a first locator associated with a first error control device merged with a second locator associated with a second error control device, wherein the first buddy line is further extended into a second buddy line by merging a third locator with the first and second locators if a second failure of the first memory device or a second memory device is predictively detected, wherein each of the first and second error control devices comprises an error-correction code (ECC) device having at least one of a parity and a locator.
Dependencies are inferred from the claim text.