DRAM test architecture for wide I/O DRAM based 2.5D/3D system chips
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorSandeep Kumar Goel
Life of this patent
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Abstract
A 2.5D or 3D test architecture includes a logic die, and a memory die. In the 2.5D architecture, the logic die and memory die are mounted on an interposer. In the 3D architecture, the memory die is mounted on the logic die. The logic die includes a control logic wrapped with a processor wrapper. The processor wrapper enables testing components of the control logic. The memory die is also mounted on the interposer. The memory die includes dynamic random access memory and channel selection/bypass logic. The control logic is coupled to the dynamic random access memory via the channel selection/bypass logic, the channel selection/bypass logic being controlled by the processor wrapper.
Claims20
A 2.5D test architecture comprising:
- an interposer mounted on a package substrate;
- a logic die mounted on the interposer, the logic die including a control logic wrapped with a processor wrapper, the processor wrapper being configured to enable testing components of the control logic;
- a memory die mounted on the interposer, the memory die including dynamic random access memory and channel selection/bypass logic, the control logic is coupled to the dynamic random access memory via the channel selection/bypass logic, the channel selection/bypass logic being controlled by the processor wrapper.
A 3D test architecture comprising:
- a logic die mounted on a package substrate, the logic die including a control logic wrapped with a processor wrapper, the processor wrapper being configured to enable testing components of the control logic;
- a memory die mounted on the logic die, the memory die including dynamic random access memory and channel selection/bypass logic, the control logic is coupled to the dynamic random access memory via the channel selection/bypass logic, the channel selection/bypass logic being controlled by the processor wrapper.
A method comprising:
- mounting an interposer on a package substrate;
- mounting a logic die on the interposer, the logic die including a control logic wrapped with a processor wrapper, the processor wrapper being configured to enable testing components of the control logic;
- mounting a memory die on the interposer, the memory die including dynamic random access memory and channel selection/bypass logic, the control logic is coupled to the dynamic random access memory via the channel selection/bypass logic, the channel selection/bypass logic being controlled by the processor wrapper.
Dependencies are inferred from the claim text.