Methods and systems for performing scan testing to identify logic device defects
AssigneeAdvanced Micro Devices, Inc.
InventorAngel Socarras
Life of this patent
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Abstract
Provided is a method of testing a logic device. The method includes comparing a first test pattern provided at an input of a first chain of logic device sub-modules with an output from the first chain to determine first type failures and comparing a second test pattern provided at an input of a second chain of logic device sub-modules with an out from the second chain to determine second type failures. An occurrence of one of the first type failures renders the logic device inoperable. An occurrence of the second type of failures is tolerated.
Claims15
A method of testing a logic device, comprising:
- comparing a first test pattern received at an input of a first chain of logic device sub-modules with a first output from the first chain of logic devices, the first output being a first pattern transmitted through the first chain of logic devices, to determine whether a first type of logic sub-module failure has occurred;
- and
- comparing a second test pattern received at an input of a second chain of logic device sub-modules with a second output from the second chain of logic devices, the second output being a second pattern transmitted through the second chain of logic devices, to determine whether a second type of logic sub-module failure has occurred;
- wherein an occurrence of both the first and the second type of logic sub-module failure renders the logic device inoperable.
A testable logic device comprising:
- a first plurality of interconnected logic sub-modules, the first plurality having a first input port and a first output port;
- and
- a second plurality of interconnected logic sub-modules, the second plurality having a second input port and a second output port;
- wherein the first plurality of interconnected logic sub-modules is configured for:
- receiving a first test pattern at the first input port,
- transmitting the first test pattern through the first plurality of interconnected logic sub-modules to the first output port, and
- comparing the first test pattern at the first output port with the first test pattern received at the first input port to determine whether a first type of logic sub-module failure has occurred,
- wherein the second plurality of interconnected logic sub-modules is configured for:
- receiving a second test pattern at the second input port,
- transmitting second test pattern through the second plurality of interconnected logic sub-modules to the second output port, and
- comparing the second test pattern at the first output port with the second test pattern received at the second, input port to determine whether a second type of logic sub-module failure has occurred, and
- wherein the first and second test patterns are used for determining defects within the first and second plurality of interconnected logic sub-modules respectively.
A method of testing a logic device, comprising:
- comparing a first test pattern provided at an input of a first chain of logic device sub-modules with an output from the first chain of logic devices to determine a first type of failure;
- and
- comparing a second test pattern provided at an input of a second chain of logic device sub-modules with an out from the second chain of logic devices to determine a of second type failure;
- wherein an occurrence of both the first and the second type failure renders the logic device inoperable and wherein the testing occurs during register transfer level design.
Dependencies are inferred from the claim text.