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US 8,914,690 B2Granted
Multi-core processor having disabled cores
AssigneePact Xpp Technologies AG
InventorsMartin Vorbach, Robert Munch
Life of this patent
Estimating the term…
Abstract
A multi-core processor having a cache, an interconnect system selectively connecting the cache to individual cores, and a interconnect control whereby selected cores are disabled.
Claims5
Apparatus, comprising:
- a processor having a plurality of data processing cores;
- an interconnect system whereby data processing cores may be selectively connected to a cache memory system, whereby the cores may receive instructions and data;
- an interconnect control operatively connected to the interconnection system to define whether selected ones of the data processing cores are connected to the cache memory system, whereby individual data processing cores are selectively disabled.
An Integrated Circuit Data Processor comprising:
- a plurality of data processing cores,
- each of the plurality of data processing cores comprises at least one Arithmetic and Logic unit;
- at least one cache memory system;
- and
- an interconnect connecting the plurality of the cores to said cache memory;
- wherein
- the interconnect is configured during manufacturing such that at least one of the plurality of data processing cores is not connected to the cache memory system thereby disabling said at least one of the plurality of data processing cores, so that not all of the data processing cores can connect to the cache memory system and function as data processing cores.
4 more elements
Dependencies are inferred from the claim text.