System and method of reducing test time via address aware BIST circuitry

A computer implemented method of executing a built-in self-test (BIST) operation on a plurality of integrated circuit memory arrays having a common BIST control unit, said method comprising:

• initiating a first BIST sequence on said plurality of integrated circuit memory arrays, using a computerized device;
• starting from a common starting point, automatically incrementing each address for each said integrated circuit memory array in common from said common starting point, using said computerized device;
• receiving, by said computerized device from each said integrated circuit memory array, a signal indicating a maximum valid address has been reached, said computerized device receiving a plurality of maximum valid addresses;
• recording said maximum valid address for each of said integrated circuit memory arrays, using said computerized device;
• determining a single relatively highest maximum valid address from said plurality of maximum valid addresses, using said computerized device;
• engaging a first mode in each said integrated circuit memory array having reached said maximum valid address, using said computerized device, said first mode preventing BIST testing;
• initiating a second BIST sequence on said plurality of integrated circuit memory arrays based on said signal indicating said maximum valid address in said integrated circuit memory array having been received from all said integrated circuit memory arrays connected to said common BIST control unit, using said computerized device;
• decrementing, starting from said single relatively highest maximum valid address, an address count for each said integrated circuit memory array, using said computerized device;
• and
• disengaging said first mode for each said integrated circuit memory array as said address count passes said maximum valid address associated with each said integrated circuit memory array during said decrementing, using said computerized device.

An apparatus for executing a built-in self-test (BIST) on integrated circuit memory arrays, comprising:

• a BIST Engine comprising:
• a test pattern generator;
• an address counter;
• a control unit;
• and
• a plurality of memory storage elements,
• said control unit being operatively coupled to a plurality of integrated circuit memory arrays, each said integrated circuit memory array comprising:
• sensing logic for comparing a received address to a maximum valid address for said integrated circuit memory array;
• and
• a signal generator generating a signal based on said maximum valid address being reached,
• said control unit generating and transmitting a first test pattern to each said integrated circuit memory array,
• said control unit sequentially incrementing or decrementing said address counter, generating and transmitting another test pattern to each said integrated circuit memory array,
• said control unit receiving said signal indicating said maximum valid address has been reached for each said integrated circuit memory array,
• said control unit storing said maximum valid address for each of said integrated circuit memory arrays in one of said plurality of memory storage elements, and
• said control unit determining all said integrated circuit memory arrays have indicated that said maximum valid address has been reached.

A computer program product for executing a built-in self-test (BIST) operation, said computer program product comprising a non-transitory computer readable storage medium having program code embodied therewith, the program code being readable and executable by a computer to perform a method comprising:

• initiating a first built-in self-test (BIST) sequence on a plurality of integrated circuit memory arrays having a common BIST control unit;
• incrementing each address for each said integrated circuit memory array in common from a common starting point;
• receiving from each said integrated circuit memory array a signal indicating a maximum valid address in said integrated circuit memory array is reached to receive a plurality of maximum valid addresses;
• recording said maximum valid addresses;
• determining a single relatively highest maximum valid address from said maximum valid addresses;
• engaging a first mode in each said integrated circuit memory array having reached said maximum valid address, said first mode preventing BIST testing;
• initiating a second BIST sequence on said plurality of integrated circuit memory arrays having said common BIST control unit, based on having received said signal indicating a maximum valid address in said integrated circuit memory array is reached from all said integrated circuit memory arrays connected to said common BIST control unit;
• decrementing an address count from said single relatively highest maximum valid address;
• and
• disengaging said first mode for each said integrated circuit memory array as said address count reaches each of said maximum valid addresses of each of said integrated circuit memory arrays during said decrementing.