Providing test coverage of integrated ECC logic en embedded memory

An apparatus, comprising:

• a memory device;
• an error correcting code (ECC) circuit communicatively coupled to the memory device;
• a first switching device communicatively coupled to the memory device and a first portion of the ECC circuit, the first switching device being configured to select at least one of a first input signal or a second input signal;
• a second switching device communicatively coupled to the memory device and a second portion of the ECC circuit, the second switching device being configured to select at least one of a signal from the memory device or a signal from the second portion of the ECC circuit, wherein the signal from the memory device and the signal from the second portion of the ECC circuit are related to at least one of the first input signal or the second input signal;
• a first error generating device communicatively coupled to at least one of the memory device or the first switching device, the first error generating device being configured to insert an error into a stream of data;
• and
• a third switching device communicatively coupled to the first error generating device, to the memory device and to at least one of the second portion of the ECC circuit or the first switching device, the third switching device being configured to select at least one of an output of the first error generating device and at least one of data from the memory device or an output of the first switching device.

A non-transitory, computer readable storage device encoded with data that, when implemented in a manufacturing facility, configures the manufacturing facility to create an apparatus, where the apparatus comprises:

• a memory device;
• an error correcting code (ECC) circuit communicatively coupled to the memory device;
• a first switching device communicatively coupled to the memory device and a first portion of the ECC circuit, the first switching device being configured to select at least one of a first input signal or a second input signal;
• a second switching device communicatively coupled to the memory device and a second portion of the ECC circuit, the second switching device being configured to select at least one of a signal from the memory device or a signal from the second portion of the ECC circuit, wherein the signal from the memory device and the signal from the second portion of the ECC circuit are related to at least one of the first input signal or the second input signal;
• a first error generating device communicatively coupled to at least one of the memory device or the first switching device, the first error generating device being configured to insert an error into a stream of data;
• and
• a third switching device communicatively coupled to the first error generating device, to the memory device and to at least one of the second portion of the ECC circuit or the first switching device, the third switching device being configured to select at least one of an output of the first error generating device and at least one of data from the memory device or an output of the first switching device.

A non-transitory, computer readable program storage device encoded with instructions that, when executed by a processing device, perform a method, where the method comprises:

• performing a first error test on a memory, the memory comprising an integrated error correcting code (ECC) portion, wherein the functionality of the ECC portion is bypassed during the first error test;
• performing a second error test of the memory, wherein the second error test includes testing the functionality of the ECC portion and performing an ECC test upon at least a portion of ECC data;
• inserting at least one error bit into the ECC data during the performance of the second error test;
• performing the second error test one or more additional times;
• and
• shifting the at least one error bit across the ECC data for each of the one or more additional times the second error test is performed.