Integrated circuit including a programmable logic analyzer with enhanced analyzing and debugging capabilities and a method therefor

An apparatus, comprising:

• an integrated circuit, comprising:
• logic analyzer circuitry having a first input receiving a plurality of signals from one or more portions of the apparatus under test, the plurality of signals being available to the logic analyzer circuitry for sampling and event triggering, and a first output for providing selected samples of the plurality of signals appearing at the first input;
• and
• a first block having a first input coupled to the logic analyzer circuitry for receiving one or more of the plurality of signals appearing at the first input thereof, and circuitry for generating a distinct set of one or more test signals based upon the one or more of the plurality of signals appearing at the first input of the first block according to a predetermined function, the predetermined function being configurable, the distinct set of one or more test signals being different from the plurality of signals received by the logic analyzer circuitry and from the one or more plurality of signals received by the first block, appearing at an output of the first block, and being provided to the logic analyzer circuitry for at least one of sampling of the distinct set of one or more test signals and event triggering;
• wherein the logic analyzer circuitry includes a second output for providing an indication of a detection, by the logic analyzer circuitry, of at least one trigger event, wherein the first block includes a second input coupled to the second output of the logic analyzer circuitry, wherein the first block generates the distinct set of one or more test signals based upon the signals received at the first and second inputs thereof, and wherein the first block is configurable as an accumulator, the accumulator being enabled by the second output of the logic analyzer circuitry, the distinct set of one or more test signals output from the accumulator is provided to the logic analyzer circuitry for at least one of sampling thereof and triggering an event by the logic analyzer.

An integrated circuit, comprising:

• logic analyzer circuitry having a first input receiving a plurality of signals, the plurality of signals being available to the logic analyzer circuitry for sampling and event triggering, and a first output for providing selected samples of the plurality of signals appearing at the first input;
• and
• a first block having a first input coupled to the logic analyzer circuitry for receiving one or more of the signals appearing at the first input thereof, circuitry for generating a distinct set of one or more signals based upon the received one or more signals appearing at the first input of the logic analyzer and according to a predetermined function, the predetermined function being configurable, and an output coupled to a second input of the logic analyzer circuitry for directly providing the generated distinct set of one or more signals to the logic analyzer circuitry as additional test signals for at least one of sampling thereof and event triggering;
• wherein the first block is configurable as an accumulator for counting a number of events detected by the logic analyzer circuitry, the first block configured to begin accumulating upon receiving a signal indicating a detection of an occurrence of an event by the logic analyzer circuitry.

A system, comprising:

• an integrated circuit, comprising:
• an embedded logic analyzer block having an input for receiving a plurality of signals from one or more portions of the system under test for sampling and event triggering, and a trigger event block for detecting an occurrence of an event based in part upon the plurality of signals;
• and
• a block having a first input coupled to the embedded logic analyzer block for receiving one or more of the plurality of signals, a second input coupled to the trigger event block for receiving a signal indicating the detection of the occurrence of the event, circuitry for generating a distinct set of one or more signals based upon the signal indicating the detection of the occurrence of the event, the distinct set of one or more signals being different from the plurality of signals appearing at the input of the embedded logic analyzer block and from the one or more of the plurality of signals received at the first input of the block, and an output for providing the generated distinct set of one or more signals to the embedded logic analyzer block as additional test signals for at least one of sampling thereof and event triggering,
• wherein the block is configurable as an accumulator for counting a number of events detected by the trigger event block, the block configured to begin accumulating upon receiving the signal indicating the detection of the occurrence of the event.

An apparatus, comprising:

• an integrated circuit, comprising:
• logic analyzer circuitry having a first input receiving a plurality of signals from one or more portions of the apparatus under test, the plurality of signals being available to the logic analyzer circuitry for sampling and event triggering, and a first output for providing selected samples of the plurality of signals appearing at the first input;
• and
• a first block having a first input coupled to the logic analyzer circuitry for receiving one or more of the plurality of signals appearing at the first input thereof, and circuitry for generating a distinct set of one or more test signals based upon the one or more of the plurality of signals appearing at the first input of the first block according to a predetermined function, the predetermined function being configurable, the distinct set of one or more test signals being different from the plurality of signals received by the logic analyzer circuitry and from the one or more plurality of signals received by the first block, appearing at an output of the first block, and being provided to the logic analyzer circuitry for at least one of sampling of the distinct set of one or more test signals and event triggering;
• wherein the first block is configured to count a number of events detected by the logic analyzer circuitry upon receiving a signal indicating a detection of an occurrence of an event by the logic analyzer circuitry, and provide the number of events to the logic analyzer circuitry for at least one of sampling thereof and event triggering.

An integrated circuit, comprising:

• logic analyzer circuitry having a first input receiving a plurality of signals, the plurality of signals being available to the logic analyzer circuitry for sampling and event triggering, and a first output for providing selected samples of the plurality of signals appearing at the first input;
• and
• a first block having a first input coupled to the logic analyzer circuitry for receiving one or more of the signals appearing at the first input thereof, circuitry for generating a distinct set of one or more signals based upon the received one or more signals appearing at the first input of the logic analyzer and according to a predetermined function, the predetermined function being configurable, and an output coupled to a second input of the logic analyzer circuitry for directly providing the generated distinct set of one or more signals to the logic analyzer circuitry as additional test signals for at least one of sampling thereof and event triggering;
• wherein the first input of the first block is coupled to the first output of the logic analyzer circuitry such that the first block receives one or more of the selected samples of the plurality signals appearing at the first input of the logic analyzer circuitry, and generates the distinct set of one or more test signals based upon the one or more selected samples.