Multicore processor power credit management in which multiple processing cores use shared memory to communicate individual energy consumption

A method for operating a microprocessor comprising two or more processing cores on a microprocessor package in a system having a memory accessible by all of the processing cores, each processing core configured with adaptive power throttling logic to operate at an adjustable operating frequency, the method comprising:

• computing a first value, by a processing core of the two or more processing cores, in response to detecting an occurrence of a power event, wherein the first value represents an amount of energy consumed by the processing core during a time interval leading up to the power event, wherein the length of the time interval is a predetermined time value;
• writing the first value to the memory;
• reading, by the processing core, one or more second values from the memory, wherein the one or more second values represent an amount of energy consumed by the other(s) of the two or more processing cores during approximately the time interval, wherein the one or more second values were previously computed and written to the memory by the other(s) of the two or more processing cores;
• adjusting, by the processing core, the operating frequency of the processing core, independently of the operating frequency of the other(s) of the two or more processing cores, based on the first value and the one or more second values;
• wherein said computing the first value comprises using a dynamic power constant of the processing core, determined during manufacture of the microprocessor package, that is multiplied by a frequency and by a square of a voltage at which the processing core operates during the time interval leading up to the power event;
• and
• wherein the one or more second values of the other(s) of the two or more processing cores were computed using a dynamic power constant of the other(s) of the two or more processing cores, determined during manufacture of the microprocessor package, that is multiplied by a frequency and by a square of a voltage at which the other(s) of the two or more processing cores operate during approximately the time interval.

A computer program product encoded in at least one non-transitory computer readable storage medium for use with a computing device, the computer program product comprising:

• computer readable program code embodied in said medium, for specifying a microprocessor configured to operate in a system having a memory, the computer readable program code comprising:
• program code for specifying two or more processing cores on a microprocessor package, wherein each processing core of the two or more processing cores is configured with adaptive power throttling logic to:
• operate at an adjustable operating frequency;
• compute a first value, in response to detecting an occurrence of a power event, wherein the first value represents an amount of energy consumed by the processing core during a time interval leading up to the power event, wherein the length of the time interval is a predetermined time value;
• write the first value to memory;
• read one or more second values from the memory, wherein the one or more second values represent an amount of energy consumed by the other(s) of the two or more processing cores during approximately the time interval, wherein the one or more second values were previously computed and written to the memory by the other(s) of the two or more processing cores;
• adjust the operating frequency of the processing core, independently of the operating frequency of the other(s) of the two or more processing cores, based on the first value and the one or more second values;
• wherein the adaptive power throttling logic of the processing core computes the first value using a dynamic power constant of the processing core, determined during manufacture of the microprocessor package, that is multiplied by a frequency and by a square of a voltage at which the processing core operates during the time interval leading up to the power event;
• and
• wherein the adaptive power throttling logic of the other(s) of the two or more processing cores computes the one or more second values using a dynamic power constant of the other(s) of the two or more processing cores, determined during manufacture of the microprocessor package, that is multiplied by a frequency and by a square of a voltage at which the other(s) of the two or more processing cores operate during approximately the time interval.