Dynamically adjusting power of non-core processor circuitry including buffer circuitry

A method comprising:

• quiescing a plurality of cores of a first frequency domain of a processor;
• blocking a plurality of interfaces between the first frequency domain and a second frequency domain of the processor:
• blocking a first unit in the first frequency domain from sending transactions to a boundary unit coupled between the first frequency domain and the second frequency domain responsive to a block signal from a power control unit (PCU) of the processor;
• receiving an acknowledgement from the first unit that the first unit has blocked sending the transactions to the boundary unit responsive to the block signal;
• stopping the boundary unit responsive to determining that the boundary unit is empty of transactions;
• and
• gating a plurality of clocks of the first frequency domain on a common clock edge and changing a frequency of the plurality of clocks from a first clock frequency to a second clock frequency, without draining the first unit of transactions.

A system comprising:

• a first multicore processor including a variable frequency domain having a plurality of cores and system agent circuitry separate from the plurality of cores, and a power control unit (PCU) including a frequency control logic to cause a frequency of the variable frequency domain to change without draining the variable frequency domain of pending transactions received from a plurality of sources, stop a plurality of clocks of the variable frequency domain at a common clock edge, and update a frequency of the variable frequency domain while the plurality of clocks are stopped;
• a second multicore processor coupled to the first multicore processor;
• and
• a first portion of a system memory coupled to the first multicore processor and a second portion of the system memory coupled to the second multicore processor.