Processing unit that detects manipulations thereof, device comprising two processing units, method for testing a processing unit and a device comprising two processing units

A device comprising:

• a main memory storing a first instruction;
• a first processing unit and a second processing unit, wherein the first and second processing units are configured such that n clock cycles passes between a jump operation to the first instruction and the execution of an operations code of the first instruction once the first instruction is stored in an instruction register, wherein n is a number,
• the first processing unit comprising a first control unit, wherein the first control unit is configured to execute after a reset phase during the n clock cycles a first sequence of test instructions to generate an output;
• the second processing unit comprising a second control unit, wherein the second control unit is configured to execute after a reset phase during the n clock cycles a second sequence of test instructions to generate an output;
• and
• a comparator, configured to compare the output of the first processing unit and the output of the second processing unit and to generate a comparison signal indicating, whether the output of the first processing unit is different to the output of the second processing unit;
• wherein a manipulation of the first or second processing unit is detected, before the control unit of the first and/or second processing unit decodes the first instruction, based on a value of the comparison signal of the comparator,
• wherein the first and second control units are configured to execute the sequence of test instructions in a hard-wired or micro-coded manner independent of program counters and instruction registers of the first and second processing units.

A method for testing a device comprising a main memory, the method comprising:

• providing the device comprising the main memory storing a first instruction, a first processing unit and a second processing unit, wherein the first and second processing units are configured such that n clock cycles passes between a jump operation to the first instruction and the execution of an operations code of the first instruction once the first instruction is stored in an instruction register, wherein n is a number,
• executing, by a first control unit of the first processing unit of the device, a first sequence of test instructions to generate a first output after a reset phase during the n clock cycles and before decoding the first instruction;
• executing, by a second control unit of the second processing unit of the device, a second sequence of test instructions to generate a second output after a reset phase during the n clock cycles and before decoding the first instruction;
• comparing the output of the first processing unit and the output of the second processing unit and to generate a comparison signal indicating, whether the output of the first processing unit is different to the output of the second processing unit;
• and
• detecting after the reset phase and before the processing units decode the first instruction for the normal operation that the first or second processing unit has been manipulated based on a value of the comparison signal,
• wherein the first and second control units are configured to execute the sequence of test instructions in a hard-wired or micro-coded manner independent of program counters and instruction registers of the first and second processing units.