Instruction set architecture-based inter-sequencer communications with a heterogeneous resource

A method comprising:

• communicating architectural state information from a user-level application executing on a first instruction sequencer of a multi-core processor to an accelerator of the multi-core processor via a first user-level instruction to configure the accelerator, wherein the accelerator comprises a heterogeneous resource with respect to the first instruction sequencer and having next instruction pointer logic to determine a next instruction to be executed by the accelerator;
• communicating a request from the user-level application to the accelerator via a second user-level instruction;
• providing the request to the accelerator via an interface logic associated with the accelerator, wherein the interface logic translates the request;
• and
• performing a first function in the accelerator responsive to the request in parallel with a second function in the first instruction sequencer, the second function orthogonal to the first function.