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US 8,914,617 B2Granted
Tracking mechanism coupled to retirement in reorder buffer for indicating sharing logical registers of physical register in record indexed by logical register
AssigneeIntel Corporation
InventorsShlomo Raikin, David J. Sager, Zeev Sperber, Evgeni Krimer, Ori Lempel, Stanislav Shwartsman, Adi Yoaz, Omer Golz
Life of this patent
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Abstract
Methods and apparatus relating to a hardware move elimination and/or next page prefetching are described. In some embodiments, a logic may provide hardware move eliminations based on stored data. In an embodiment, a next page prefetcher is disclosed. Other embodiments are also described and claimed.
Claims20
A processor comprising:
- a first storage unit having a plurality of physical registers to store content for a physical register as an entry;
- a second storage unit to store one or more pointers, indexed according to one or more logical registers, that map said one or more logical registers to a physical register corresponding to the entry;
- a Reorder Buffer (ROB) to store information about an in flight instruction or micro-operation to facilitate retirement of the in flight instruction or micro-operation;
- a tracking mechanism operatively coupled with retirements in the ROB to track sharing in time of any entries in the first storage unit, to which more than one of the logical registers map, by a record, indexed according to said more than one of the logical registers, and indicating for every shared entry of the plurality of physical registers which of the logical registers are currently sharing it;
- and
- logic to cause one of the one or more pointers to point to the entry and to update the record indexed by a logical register corresponding to said one of the one or more pointers in response to a request to copy content of the entry to said logical register.
3 more elements
A system comprising:
- a memory to store one or more instructions;
- and
- a processor to execute the one or more instructions, wherein the processor is to comprise at least one processor core comprising:
- a first storage unit having a plurality of physical registers to store content for a physical register as an entry;
- a second storage unit to store one or more pointers, indexed according to one or more logical registers, that map said one or more logical registers to a physical register corresponding to the entry;
- a Reorder Buffer (ROB) to store information about an in flight instruction or micro-operation to facilitate retirement of the in flight instruction or micro-operation;
- a tracking mechanism operatively coupled with retirements in the ROB to track sharing in time of any entries in the first storage unit, to which more than one of the logical registers map, by a record, indexed according to said more than one of the logical registers, and indicating for every shared entry of the plurality of physical registers which of the logical registers are currently sharing it;
- and
- logic to cause one of the one or more pointers to point to the entry and to update the record indexed by a logical register corresponding to said one of the one or more pointers in response to a request to copy content of the entry to said logical register.
6 more elements
A method comprising:
- storing content for a physical register as an entry in a first storage unit having a plurality of physical registers;
- storing in a second storage unit, one or more pointers indexed according to one or more logical registers to map said one or more logical registers to a physical register corresponding to the entry;
- storing information in a Reorder Buffer (ROB) about an in flight instruction or micro-operation to facilitate retirement of the in flight instruction or micro-operation;
- tracking in time, in a mechanism operatively coupled with retirements in the ROB, sharing of any entries in the first storage unit, to which more than one of the logical registers map, by a record, indexed according to said more than one of the logical registers, and indicating for every shared entry of the plurality of physical registers which of the logical registers are currently sharing it;
- and
- causing one of the one or more pointers to point to the entry and to update the record indexed by a logical register corresponding to said one of the one or more pointers in response to a request to copy content of the entry to said logical register.
3 more elements
Dependencies are inferred from the claim text.