Mapping same logical register specifier for different instruction sets with divergent association to architectural register file using common address format

Apparatus for processing data comprising:

• processing means for performing processing operations;
• a plurality of architectural register means for storing operand values;
• first decoder means for decoding program instructions of a first instruction set to generate control signals for controlling said processing means to perform processing operations;
• and
• second decoder means for decoding program instructions of a second instruction set to generate control signals for controlling said processing means to perform processing operations;
• wherein
• program instructions of said first instruction set include first logical register specifiers specifying first logical register means for holding operand values, said first logical register means corresponding to architectural register means and having a plurality of different sizes corresponding to different numbers of words of data up to a maximum number of words of data;
• program instructions of said second instruction set include second logical register specifiers specifying second logical register means for holding operand values, said second logical register means corresponding to architectural register means and having a plurality of different sizes corresponding to different numbers of words of data up to said maximum number of words of data;
• said first decoder means maps said first logical specifiers using a first mapping to a common address format;
• said second decoder means maps said second logical specifiers using a second mapping to said common address format;
• and
• said second mapping is divergent from said first mapping wherein at least some values used as both a first logical register specifier and a second logical register specifier map to different architectural register means.

A method of processing data comprising the steps of:

• performing processing operations with processing circuitry;
• storing operand values in a plurality of architectural registers of an architectural register file;
• decoding program instructions of a first instruction set to generate control signals for controlling said processing circuitry to perform processing operations;
• and
• decoding program instructions of a second instruction set to generate control signals for controlling said processing circuitry to perform processing operations;
• wherein
• program instructions of said first instruction set include first logical register specifiers specifying first logical registers holding operand values, said first logical registers corresponding to architectural registers within said architectural register file and having a plurality of different sizes corresponding to different numbers of words of data up to a maximum number of words of data;
• program instructions of said second instruction set include second logical register specifiers specifying second logical registers holding operand values, said second logical registers corresponding to architectural registers within said architectural register file and having a plurality of different sizes corresponding to different numbers of words of data up to said maximum number of words of data;
• further comprising the steps of:
• using a first mapping to map said first logical specifiers to a common address format;
• and
• using a second mapping to map said second logical specifiers to said common address format;
• wherein
• said second mapping is divergent from said first mapping wherein at least some values used as both a first logical register specifier and a second logical register specifier map to different architectural registers.