Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bits

A computer implemented method for shuffling packed data elements comprising:

• decoding a single instruction specifying a field of per-lane control bits, and indicating a first source operand, a second source operand, and a destination operand, said first source, second source and destination operands having corresponding pluralities of multi-bit lanes, the corresponding multi-bit lanes each including a same number of data elements;
• responsive to decoding the single instruction, selecting a set of data elements including data elements from every multi-bit lane of the first source operand and data elements from every multi-bit lane of the second source operand according to the field of per-lane control bits, the selecting including selecting a first data element from a first lane of the first source operand and selecting a second data element from a second lane of the first source operand with a same first plurality of bits of the per-lane control bits;
• and
• storing the selected set of data elements to the destination operand.

A processor comprising:

• a decode unit to decode a single instruction indicating per-lane control bits, a source operand, and a destination operand, the source operand and the destination operand each having first and second lanes;
• and
• an execution unit including hardware, the execution unit based on the decoding of the single instruction to shuffle data elements from the first lane of the source operand to the first lane of the destination operand according to the per-lane control bits and to shuffle data elements from the second lane of the source operand to the second lane of the destination operand according to the per-lane control bits,
• wherein a same plurality of bits of the per-lane control bits is used to shuffle both a first data element of the first lane of the source operand to the destination operand and also a second data element of the second lane of the source operand to the destination operand, the first data element and the second data element in same relative positions in the first and second lanes of the source operand.

A processor comprising:

• a decode unit to decode an instruction indicating a source operand, indicating a destination operand, and indicating per-lane control bits, each of the source and destination operands having a first lane and a second lane, each of the first and second lanes of the source and destination operands having an upper portion and a lower portion, the upper portion of the first lane of the source operand having data elements D, C, B, and A, the lower portion of the first lane of the source operand having a first plurality of data elements, the upper portion of the second lane of the source operand having data elements H, G, F, and E, the lower portion of the second lane of the source operand having a second plurality of data elements;
• and
• an execution unit coupled with the decode unit, the execution unit including circuitry, the execution unit as a result of the decode unit decoding the instruction to copy any of the data elements D-A specified by a first plurality of the per-lane control bits to a first data element of the upper portion of the first lane of the destination operand, copy any of the data elements D-A specified by a second plurality of the per-lane control bits to a second data element of the upper portion of the first lane of the destination operand, copy any of the data elements D-A specified by a third plurality of the per-lane control bits to a third data element of the upper portion of the first lane of the destination operand, copy any of the data elements D-A specified by a fourth plurality of the per-lane control bits to a fourth data element of the upper portion of the first lane of the destination operand, and
• copy any of the data elements H-E specified by the first plurality of the per-lane control bits to a first data element of the upper portion of the second lane of the destination operand, copy any of the data elements H-E specified by the second plurality of the per-lane control bits to a second data element of the upper portion of the second lane of the destination operand, copy any of the data elements H-E specified by the third plurality of the per-lane control bits to a third data element of the upper portion of the second lane of the destination operand, copy any of the data elements H-E specified by the fourth plurality of the per-lane control bits to a fourth data element of the upper portion of the second lane of the destination operand.