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US 8,914,612 B2Granted
Data processing with time-based memory access
AssigneeConversant Intellectual Property Management Inc.
InventorNagi N. Mekhiel
Life of this patent
Estimating the term…
Abstract
Memory access in data processing is provided using a time-based technique in which memory locations are mapped to respectively corresponding periods of time during which they are made available for access.
Claims35
A method of providing a data processor with access to a plurality of memory locations in a memory, comprising:
- independently of the data processor, accessing the memory locations sequentially and repetitively to produce a continually repeating sequence of memory location accesses;
- and
- making said continually repeating sequence of memory location accesses available to the data processor.
A method of providing a plurality of data processors with shared access to a memory having a plurality of memory locations, comprising:
- independently of the data processors, accessing a first group of the memory locations sequentially and repetitively to produce a first continually repeating sequence of memory location accesses;
- making said first continually repeating sequence of memory location accesses available to a first one of the data processors;
- independently of the data processors, accessing a second group of the memory locations sequentially and repetitively to produce a second continually repeating sequence of memory location accesses;
- and
- making said second continually repeating sequence of memory location accesses available to a second one of the data processors.
2 more elements
A memory apparatus for use with a data processor, comprising:
- a memory having a plurality of memory locations;
- a memory controller coupled to said memory and cooperable therewith independently of the data processor for accessing said memory locations sequentially and repetitively to produce a continually repeating sequence of memory location accesses;
- and
- a bus coupled to said memory and adapted for coupling to the data processor to make said continually repeating sequence of memory location accesses available to the data processor.
1 more element
A memory apparatus for use with a plurality of data processors, comprising:
- a memory having a plurality of memory locations;
- a memory controller coupled to said memory and cooperable therewith independently of the data processors for
- accessing a first group of the memory locations sequentially and repetitively to produce a first continually repeating sequence of memory location accesses, and
- accessing a second group of the memory locations sequentially and repetitively to produce a second continually repeating sequence of memory location accesses;
- a first bus coupled to said memory and adapted for coupling to a first one of the data processors to make said first continually repeating sequence of memory location accesses available to the first data processor;
- and
- a second bus coupled to said memory and adapted for coupling to a second one of the data processors to make said second continually repeating sequence of memory location accesses available to the second data processor.
4 more elements
A data processing apparatus, comprising:
- a data processor;
- a memory having a plurality of memory locations;
- a memory controller coupled to said memory and cooperable therewith independently of said data processor for accessing said memory locations sequentially and repetitively to produce a continually repeating sequence of memory location accesses;
- and
- said memory coupled to said data processor to make said continually repeating sequence of memory location accesses available to said data processor.
2 more elements
A data processing apparatus, comprising:
- first and second data processors;
- a memory having a plurality of memory locations;
- a memory controller coupled to said memory and cooperable therewith independently of said first and second data processors for accessing a first group of the memory locations sequentially and repetitively to produce a first continually repeating sequence of memory location accesses, and accessing a second group of the memory locations sequentially and repetitively to produce a second continually repeating sequence of memory location accesses;
- said memory coupled to said first and second data processors to make said first and second continually repeating sequences of memory location accesses respectively available to said first and second data processors.
1 more element
A data processing apparatus, comprising:
- a data processor;
- a memory having a plurality of memory locations;
- a memory controller coupled to said memory and cooperable therewith independently of said data processor for accessing said memory locations sequentially and repetitively to produce a continually repeating sequence of memory location accesses;
- said memory coupled to said data processor to make said continually repeating sequence of memory location accesses available to said data processor;
- and
- a user interface coupled to said data processor to permit user access to said data processor.
3 more elements
A data processing apparatus, comprising:
- first and second data processors;
- a memory having a plurality of memory locations;
- a memory controller coupled to said memory and cooperable therewith independently of said first and second data processors for accessing a first group of the memory locations sequentially and repetitively to produce a first continually repeating sequence of memory location accesses, and accessing a second group of the memory locations sequentially and repetitively to produce a second continually repeating sequence of memory location accesses;
- said memory coupled to said first and second data processors to make said first and second continually repeating sequences of memory location accesses respectively available to said first and second data processors;
- and
- a user interface coupled to said first data processor to permit user access to said first data processor.
3 more elements
A data processing apparatus, comprising:
- a data processing portion;
- and
- a memory interface portion coupled to said data processing portion, said memory interface portion configured to interface with a memory apparatus that contains a plurality of memory locations and is operable, independently of said data processing portion and said memory interface portion, to present to said memory interface portion a continually repeating sequence of memory location accesses, and said memory interface portion further configured to make said continually repeating sequence of memory location accesses available to said data processing portion.
A method of transferring first and second vectors from a memory apparatus to a data processing apparatus, wherein said first vector includes a first plurality of vector components respectively stored in a first plurality of memory locations in the memory apparatus, and wherein said second vector includes a second plurality of vector components respectively stored in a second plurality of memory locations in the memory apparatus, comprising:
- independently of the data processing apparatus, accessing the first plurality of memory locations sequentially to provide the first plurality of vector components in a first sequence;
- sequentially loading the first vector components of the first sequence into respective data processing elements of the data processing apparatus;
- independently of the data processing apparatus, accessing the second plurality of memory locations sequentially to provide the second plurality of vector components in a second sequence;
- and
- sequentially loading the second vector components of the second sequence respectively into said data processing elements of the data processing apparatus.
2 more elements
Dependencies are inferred from the claim text.