Address translation device, processing device and control method of processing device

An address translation device, connected to a main storage device which stores page tables holding pairs of virtual addresses and physical addresses by respective page sizes each indicating a size of a page being a unit by which a translation between the virtual address and the physical address is performed and an instruction control unit which issues a memory access request, the address translation device comprising:

• an address translation buffer which holds the pairs of the virtual addresses and physical addresses by respective page sizes, and performs the translation between the virtual address and the physical address;
• a history holding unit which holds a pair of a virtual address removed from the address translation buffer and page size corresponding to the removed virtual address when a pair of a new virtual address and physical address read from the page table is registered to the address translation buffer;
• base registers which hold a base address being a part of the virtual address indicating a segment of the page by each page size;
• and
• a memory management unit which searches the address translation buffer based on a translation object virtual address included in the memory access request issued by the instruction control unit, and when a search miss occurs, searches the pairs of the virtual addresses and physical addresses held by the main storage device based on a pointer address indicating an address of the page table at the main storage device generated from the pair of the virtual address and page size held by the history holding unit and the base address held by the base register, and translates the translation object virtual address into the physical address.