US 8,914,589 B2 · Multi-port DRAM architecture for accessing different memory partitions

Abstract

Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access.

Claims33

Dependent claims

A memory device, comprising:

at least one memory array comprising a plurality of predefined sections of memory;
at least one command/address (CA) port configured to receive command and address signals from a plurality of processing units for accessing the at least one memory array, the plurality of processing units being external to the memory device;
and
a plurality of data ports, each data port being associated with a different predefined section of the memory array and being configured to transfer data to and from the section of the memory array associated therewith, wherein each of the plurality of processing units is coupled to only one of the plurality of data ports, wherein each of the plurality of processing units is configured to transfer data to and from only the data port to which the processing unit is coupled.

1 more element

Dependencies are inferred from the claim text.

Multi-port DRAM architecture for accessing different memory partitions

Life of this patent

Multi-port DRAM architecture for accessing different memory partitions

Life of this patent

Abstract

Claims33