Method and apparatus for accessing cache memory

A machine-implemented method in a cache system of a memory controller of a network processor in a network element to avoid caching data identified by physical memory addresses that have not been accessed frequently in a recent period of time, the method comprising the steps of:

• receiving a request for writing data to a memory location within a main memory identified by a physical memory address;
• incrementing, in a filter array comprising a plurality of entries that each include a value, the value of a first entry, by one count, wherein each of the plurality of entries is currently associated with one or more recently accessed physical memory addresses, wherein each of the plurality of entries can store a value larger than one, and wherein the first entry is associated with the physical memory address;
• in response to the request, accessing a cache memory based on the physical memory address to determine whether the cache memory contains a cache entry corresponding to the physical memory address, wherein entries in the cache memory are to store cache lines that have a size spanning a set of one or more physical memory addresses and that are aligned on cache line boundaries;
• writing the data to the cache entry corresponding to the physical memory address in the cache memory if there is a cache hit;
• and
• in response to a cache miss, performing the following steps:
• determining whether the value of the first entry of the filter array reaches a predetermined threshold, and
• if the value of the first entry has reached the predetermined threshold to justify creation of a cache line whose span would include the physical memory address, then performing the steps of:
• allocating a cache entry from the cache memory to cache the data;
• and
• writing the data associated with the request to the allocated cache entry;
• and
• decrementing, upon an occurrence of a predetermined number of processing cycles, the value of each of the plurality of entries of the filter array by one count, such that the value of each of the plurality of entries represents a number of accesses of corresponding physical memory locations wherein each value decays by one count upon a set period of time represented by the predetermined number of processing cycles.

A network processor, comprising:

• one or more processor cores;
• and
• a memory controller coupled to the one or more processor cores, the memory controller including,
• a cache memory having a plurality of cache entries, wherein the entries in the cache memory are to store cache lines that have a size spanning a set of one or more physical memory addresses and that are aligned on cache line boundaries,
• a cache controller, coupled to the cache memory, configured to receive read requests from the one or more processor cores for data associated with physical addresses, detect cache hits and cache misses in the cache memory, and respond with the requested data from the cache memory on cache hits and from a main memory on cache misses,
• a cache filter, coupled to the cache controller, configured to determine for each cache miss, whether the value of an entry of a filter array that is associated with the requested physical memory address reaches a predetermined threshold to justify creation of a cache line whose span would include the requested physical memory address, the cache filter comprising,
• the filter array having a plurality of entries, each entry including a value and being currently associated with one or more recently accessed physical memory addresses, wherein each of the plurality of entries can store a value larger than one,
• an increment logic coupled to the filter array to increment, for each of the received requests, the value in the filter array entry associated with the requested physical memory address by one count,
• a counter for continuously counting a predetermined number of processing cycles, and
• a decrement logic coupled to the counter to independently decrement the value in each of the entries of the filter array upon the occurrence of the predetermined number of processing cycles by one count, such that the value of each of the plurality of entries represents a number of accesses of corresponding physical memory locations wherein each value decays by one count upon a set period of time represented by the predetermined number of processing cycles, and
• wherein the cache controller is configured to allocate, for each cache miss, one of the cache entries only if there have been the predetermined number of accesses within the predetermined period of time.