Integrated circuit, system, and method including a shared synchronization bus
AssigneeSilicon Laboratories Inc.
InventorsBradley Martin, Thomas Saroshan David, Alan Lee Westwick
Life of this patent
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Abstract
An integrated circuit includes a shared synchronization bus having a plurality of channels assigned to one or more of a plurality of peripheral modules. The integrated circuit further includes a first peripheral module of the plurality of peripheral modules including a control output coupled to the shared synchronization bus and configured to communicate event timing data to an input of a second peripheral module of the plurality of peripheral modules through a selected one of the plurality of channels.
Claims19
An integrated circuit comprising:
- a shared synchronization bus including a plurality of channels assigned to one or more of a plurality of peripheral modules;
- and
- a first peripheral module of the plurality of peripheral modules including a control output coupled to the shared synchronization bus and configured to communicate event timing data to an input of a second peripheral module of the plurality of peripheral modules through a selected one of the plurality of channels to synchronize the first peripheral module and the second peripheral module to an event independent of a clock signal;
- and
- a programmable counter array (PCA) having a PCA controller, the PCA controller comprises:
- a multiplexer including a plurality of inputs to receive a respective plurality of periodic signals, a select input, a first output, and a second output;
- a clock divider including an input coupled to the first output of the multiplexer;
- and
- a counter including a first input coupled to an output of the clock divider, and a second input coupled to the second output of the multiplexer, and an output coupled to the shared synchronization bus.
An integrated circuit comprising:
- a synchronization bus including a plurality of channels;
- and
- a plurality of peripheral modules coupled to one or more of the plurality of channels, the plurality of peripheral modules including a first module and a second module configured to communicate through one of the plurality of channels to synchronize the second module to an event at the first module;
- and
- wherein each channel of the plurality of channels comprises:
- a register to store at least one reference value;
- and
- a compare module including a first input coupled to the shared synchronization bus, a second input coupled to the register, and an output.
A method comprising:
- receiving a signal indicating an event at a first module of a plurality of peripheral modules;
- communicating event timing information corresponding to the event from the first module to at least one second module of the plurality of peripheral modules through one or more channels of a plurality of channels of a shared synchronization bus to synchronize the at least one second module to the event independent of a clock signal, each channel of the plurality of channels comprises:
- a register to store at least one reference value;
- and
- a compare module including a first input coupled to the shared synchronization bus, a second input coupled to the register, and an output.
Dependencies are inferred from the claim text.