US 8,914,538 B2Granted

Implementing network manager quarantine mode

AssigneeLenovo Enterprise Solutions (Singapore) Pte. Ltd.

InventorsMarcy E. Byers, Kenneth M. Valk

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Abstract

A method and circuit for implementing a network manager quarantine mode in an interconnect system, and a design structure on which the subject circuit resides are provided. A respective network manager on a source interconnect chip and a destination interconnect chip sends end-to-end (ETE) heartbeats on each path between the source and destination interconnect chips. Each network manager maintains a heartbeat table with counters to track each path to each destination interconnect chip. When a first network manager of a first interconnect chip detects a change from at least one valid path to no working paths for a second interconnect chip of the interconnect chips, the quarantine mode is established for a programmable quarantine time interval and all paths are prevented from advertising good heartbeats during the quarantine time interval.

Claims24

Dependent claims

A method for implementing a network manager quarantine mode in an interconnect system, said method comprising:

providing a plurality of paths defined by links connected between each source interconnect chip and each destination interconnect chip;
providing each said interconnect chip with a network manager, said network manager sending end-to-end (ETE) heartbeats on said plurality of paths through the interconnect system to each destination interconnect chip;
each said network manager maintaining a heartbeat table with a respective counter to track path status of each path through the interconnect system to each destination interconnect chip;
each path being identified by a chip-identification (ID), exit port;
said heartbeat table including a respective up/down counter for each chip-ID, exit port, each said up/down counter for each chip-ID, exit port being incremented with a heartbeat being received for said chip-ID, and each said up/down counter for each chip-ID, exit port being decremented on a set interval;
first predefined counter values of each said up/down counter for each chip-ID, exit port represent a bad heartbeat and second first predefined counter values of each said up/down counter for each chip-ID, exit port represent a good heart beat;
said heartbeat table including an heartbeat return bit from a last heartbeat received, a hop count indicating a hop count of said last heartbeat received;
and an enable bit to control sending or not sending heartbeats;
said network manager of a first interconnect chip detecting a path status change from at least one valid path to no working paths for a second interconnect chip;
and
said network manager of the first interconnect chip, responsive to said detected path status change to no working paths for said second interconnect chip, establishing a quarantine mode for a programmable quarantine time interval to prevent advertising good heartbeats for each of said paths for said second interconnect chip during said programmable quarantine time interval;
said network manager of the first interconnect chip, responsive to said programmable quarantine time interval expiring, advertising good heartbeats for each of said paths for said second interconnect chip, and sending path update responsive to said paths for said second interconnect chip being indicated as good;
and
wherein each said network manager maintaining said heartbeat table with said respective counter to track status of each path through the interconnect system to each destination interconnect chip includes providing said respective up/down counter with a predefined multiple-bit counter, where a first count range represents said bad heartbeat and a second count range represents said good heartbeat, said second count range being greater than said first count range.

11 more elements

A circuit for implementing a network manager quarantine mode in an interconnect system, said circuit comprising:

an interconnect chip including a network manager, said network manager sending end-to-end (ETE) heartbeats on a plurality of paths through the interconnect system to each destination interconnect chip;
said plurality of paths defined by links connected between said interconnect chip and each said destination interconnect chip;
each said network manager maintaining a heartbeat table with a respective counter to track path status of each said path through the interconnect system to each destination interconnect chip;
each path being identified by a chip-identification (ID), exit port;
said heartbeat table including a respective up/down counter for each chip-ID, exit port, each said up/down counter for each chip-ID, exit port being incremented with a heartbeat being received for said chip-ID, and each said up/down counter for each chip-ID, exit port being decremented on a set interval;
first predefined counter values of each said up/down counter for each chip-ID, exit port represent a bad heartbeat and second first predefined counter values of each said up/down counter for each chip-ID, exit port represent a good heart beat;
said heartbeat table including an heartbeat return bit from a last heartbeat received, a hop count indicating a hop count of said last heartbeat received;
and an enable bit to control sending or not sending heartbeats;
said network manager of a first interconnect chip detecting a path status change from at least one valid path to no working paths to a second interconnect chip;
and
said network manager of the first interconnect chip, responsive to said detected path status change to no working paths to said second interconnect chip, establishing a quarantine mode for a programmable quarantine time interval to prevent advertising good heartbeats for each of said paths for said second interconnect chip during said programmable quarantine time interval;
said network manager of the first interconnect chip, responsive to said programmable quarantine time interval expiring, advertising good heartbeats for each of said paths for said second interconnect chip, and sending a path update responsive to said paths for said second interconnect chip being indicated as good;
and
wherein each said network manager maintaining said heartbeat table with said respective counter to track status of each path through the interconnect system to each destination interconnect chip includes providing said respective up/down counter with a predefined multiple-bit counter, where a first count range represents said bad heartbeat and a second count range represents said good heartbeat, said second count range being greater than said first count range.

11 more elements

A multiple-path local rack interconnect system comprising:

a plurality of interconnect chips including a source interconnect chip and a destination interconnect chip;
a plurality of paths defined by serial links connected between each of said plurality of interconnect chips;
said interconnect chips including a network manager, said network manager sending end-to-end (ETE) heartbeats on a plurality of paths through the interconnect system to each destination interconnect chip;
said plurality of paths defined by links connected between said interconnect chip and each said destination interconnect chip;
each said network manager maintaining a heartbeat table with a respective counter to track path status of each said path through the interconnect system to each destination interconnect chip;
each path being identified by a chip-identification (ID), exit port;
said heartbeat table including a respective up/down counter for each chip-ID, exit port, each said up/down counter for each chip-ID, exit port being incremented with a heartbeat being received for said chip-ID, and each said up/down counter for each chip-ID, exit port being decremented on a set interval;
first predefined counter values of each said up/down counter for each chip-ID, exit port represent a bad heartbeat and second first predefined counter values of each said up/down counter for each chip-ID, exit port represent a good heart beat;
said heartbeat table including an heartbeat return bit from a last heartbeat received, a hop count indicating a hop count of said last heartbeat received;
and an enable bit to control sending or not sending heartbeats;
said network manager of a first interconnect chip detecting a path status change from at least one valid path to no working paths to a second interconnect chip;
and
said network manager of the first interconnect chip, responsive to said detected path status change to no working paths to said second interconnect chip, establishing a quarantine mode for a programmable quarantine time interval to prevent advertising good heartbeats for each of said paths for said second interconnect chip during said programmable during said quarantine time interval;
said network manager of the first interconnect chip, responsive to said programmable quarantine time interval expiring, advertising good heartbeats for each of said paths for said second interconnect chip, and sending path update responsive to said paths for said second interconnect chip being indicated as good;
and
wherein each said network manager maintaining said heartbeat table with said respective counter to track status of each path through the interconnect system to each destination interconnect chip includes providing said respective up/down counter with a predefined multiple-bit counter, where a first count range represents said bad heartbeat and a second count range represents said good heartbeat, said second count range being greater than said first count range.

13 more elements

A design structure embodied in a non-transitory machine readable medium used in a design process, the design structure comprising:

a circuit tangibly embodied in the non-transitory machine readable medium used in the design process, said circuit for implementing a network manager quarantine mode in an interconnect system, said circuit comprising:
an interconnect chip including a network manager, said network manager sending end-to-end (ETE) heartbeats on a plurality of paths through the interconnect system to each destination interconnect chip;
said plurality of paths defined by links connected between said interconnect chip and each said destination interconnect chip;
each said network manager maintaining a heartbeat table with a respective counter to track path status of each said path through the interconnect system to each destination interconnect chip;
each said path being identified by a chip-identification (ID), exit port;
said heartbeat table including a respective up/down counter for each chip-ID, exit port, each said up/down counter for each chip-ID, exit port being incremented with a heartbeat being received for said chip-ID, and each said up/down counter for each chip-ID, exit port being decremented on a set interval;
first predefined counter values of each said up/down counter for each chip-ID, exit port represent a bad heartbeat and second first predefined counter values of each said up/down counter for each chip-ID, exit port represent a good heart beat;
said heartbeat table including an heartbeat return bit from a last heartbeat received, a hop count indicating a hop count of said last heartbeat received;
and an enable bit to control sending or not sending heartbeats;
said network manager of a first interconnect chip detecting a path status change from at least one valid path to no working paths to a second interconnect chip;
and
said network manager of the first interconnect chip, responsive to said detected path status change to no working paths to said second interconnect chip, establishing a quarantine mode for a programmable quarantine time interval to prevent advertising good heartbeats for each of said paths for said second interconnect chip during said programmable during said quarantine time interval;
said network manager of the first interconnect chip, responsive to said programmable quarantine time interval expiring, advertising good heartbeats for each of said paths for said second interconnect chip, and sending path update responsive to said paths for said second interconnect chip being indicated as good, wherein the design structure, when read and used in a manufacture of a semiconductor chip produces a chip comprising said circuit;
and
wherein each said network manager maintaining said heartbeat table with said respective counter to track status of each path through the interconnect system to each destination interconnect chip includes providing said respective up/down counter with a predefined multiple-bit counter, where a first count range represents said bad heartbeat and a second count range represents said good heartbeat, said second count range being greater than said first count range.

12 more elements

Dependencies are inferred from the claim text.