Back to results
US 8,914,430 B2Granted
Multiply add functional unit capable of executing scale, round, GETEXP, round, GETMANT, reduce, range and class instructions
AssigneeIntel Corporation
InventorsAmit Gradstein, Cristina S. Anderson, Zeev Sperber, Simon Rubanovich, Benny Eitan
Life of this patent
Estimating the term…
Abstract
A method is described that involves executing a first instruction with a functional unit. The first instruction is a multiply-add instruction. The method further includes executing a second instruction with the functional unit. The second instruction is a round instruction.
Claims17
A processor, comprising:
- an instruction execution pipeline implemented with circuitry disposed on a semiconductor chip, said instruction execution pipeline comprising:
- an instruction fetch unit to fetch instructions;
- an instruction decode unit to decode the instructions;
- and
- functional units to execute the instructions, a functional unit of the functional units to perform at least three different floating point instructions and having exponent difference calculation logic, a multiplier and an adder to support a first of the at least three different floating point instructions which is a multiply-add instruction, said functional unit also having a rounder to support a second of the at least three different floating point instructions which is a vector round instruction that specifies how many binary places each mantissa value of a vector of floating point values is to be rounded to, said exponent difference calculation logic having a shifter to support execution of said multiply-add instruction and said vector round instruction, wherein said vector round instruction is a different instruction than said multiply-add instruction, and wherein the functional unit is also able to perform at least one other instruction which is different than the multiply-add instruction and different than the vector round instruction.
2 more elements
A method, comprising:
- fetching a first of at least three different floating-point instructions with an instruction fetch unit of an instruction execution pipeline implemented with circuitry on a semiconductor chip;
- decoding said first instruction with an instruction decode unit of said instruction execution pipeline;
- executing said first instruction with a functional unit of said instruction execution pipeline, said first instruction being a multiply-add instruction;
- fetching a second of the at least three different floating point instructions with said instruction fetch unit of said instruction execution pipeline;
- decoding said second instruction with said instruction decode unit;
- executing said second instruction with said functional unit, said second instruction being a vector round instruction wherein said vector round instruction is a different instruction than said multiply-add instruction, and wherein the functional unit is also able to perform at least one other instruction which is different than the multiply-add instruction and different than the vector round instruction.
3 more elements
A computing system, comprising:
- non-volatile storage unit;
- and
- a processor, said processor having an instruction fetch unit, an instruction decode unit and a functional unit, said functional unit to perform at least three different floating point instructions and having exponent difference calculation logic, a multiplier and an adder to support a first of the at least three different floating point instructions which is a multiply-add instruction, said functional unit also having a rounder to support a second of the at least three different floating point instructions which is a round instruction that specifies how many binary places a mantissa value is to be rounded to, said exponent difference calculation logic having a shifter to support execution of said multiply-add and said round instruction, wherein the shifter is also to support a third of the at least three different floating point instructions which is a scale instruction to be executed by said functional unit, the scale instruction to scale a first floating point value by a floor of a second floating point value, and wherein said vector round instruction, said multiply-add instruction, and said scale instruction are all different instructions from each other.
Dependencies are inferred from the claim text.