Multi-channel multi-protocol transceiver with independent channel configuration using single frequency reference clock source

A communication system comprising:

• a reference clock configured to output a constant clock frequency;
• and
• a first transceiver comprising:
• a first phase lock loop system comprising:
• a first reference clock system configured to receive the constant clock frequency comprising a first adjustable divider, and
• a first phase lock loop configured to produce a first output clock frequency based on the constant clock frequency to support a first selected communications protocol of a plurality of possible communications protocols, the first phase lock loop comprising a first integer divider;
• and
• a second phase lock loop system comprising:
• a second reference clock system configured to receive the constant clock frequency comprising a second adjustable divider;
• and
• a second phase lock loop configured to produce a second output clock frequency based on the constant clock frequency to support a second selected communications protocol of the plurality of possible communications protocols, the second output clock frequency being different from the first output clock frequency and the second communications protocol being different from the first communications protocol, the second phase lock loop comprising a second integer divider,
• wherein a divisor of the first adjustable divider is different from a divisor of the second adjustable divider, or
• wherein a divisor of the first integer divider is different from a divisor of the second integer divider.

A transceiver system comprising:

• a plurality of transmitters;
• a plurality of receivers;
• and
• a plurality of phase lock loop systems, wherein each of the plurality of phase lock loop systems comprises:
• a reference clock system configured to receive a constant reference clock frequency, the reference clock system comprising:
• a bypass path,
• a divider path, the divider path including an adjustable divider configured to change a value of a divisor that divides the constant reference clock frequency, and
• a multiplexer configured to route the bypass path or the divider path based on the selected communications protocol;
• and
• a phase lock loop, the phase lock loop comprising:
• a feedback path, the feedback path including an integer divider, wherein a divisor of the integer divider is set based on a selected communications protocol, and
• a voltage controlled oscillator configured to produce one of a plurality of output clock frequencies corresponding to the selected communications protocol, wherein the one of the plurality of output clock frequencies is produced based on at least one of the routings of the multiplexer, a divisor of the adjustable divider, and the divisor of the integer divider,
• wherein:
• each reference clock system of each of the plurality of phase lock loop systems receives the constant reference clock frequency from a single reference clock;
• and
• the divisor of the adjustable divider is different from a divisor of each other adjustable divider of the plurality of phase lock loop systems;
• or
• the divisor of the integer divider of the phase lock loop is different from a divisor of each other integer divider of the plurality of phase lock loop systems.