Method and system for jitter reduction
AssigneeInfineon Technologies AG
InventorsDietmar Koenig, Harald Schmid, Thomas Steinecke
Life of this patent
Estimating the term…
Abstract
Embodiments relate to systems and methods for reducing jitter caused by frequency modulation of a clock signal including modulating the frequency of the clock signal based on a predetermined modulation signal m(t), and compensating an accumulated jitter J(t) caused by the frequency modulation of the clock signal such that an absolute value of the accumulated jitter J(t) never exceeds a predetermined jitter limit Jlim.
Claims24
A system for reducing jitter caused by frequency modulation of a clock signal comprising:
- a clock signal source configured to generate the clock signal with a frequency fCLK;
- a frequency modulator configured to modulate the frequency of the clock signal by subtracting a predetermined time varying non-negative clock period error signal t(t) from a clock period TCLK=1/fCLK of the clock signal to cause a non-positive accumulated jitter J(t) of the clock signal over time;
- a detector configured to detect whenever an absolute value of the accumulated jitter J(t) reaches a predetermined jitter limit Jlim;
- and
- a clock signal modifier configured to modify the clock signal effecting a positive phase shift of the clock signal corresponding to the predetermined jitter limit Jlim whenever the absolute value of the accumulated jitter J(t) reaches the predetermined jitter limit Jlim.
A system comprising:
- a circuit configured to cause a predetermined constantly non-positive additional accumulated jitter J(t) of a clock signal by frequency modulation of the clock signal;
- a detector circuit configured to detect, after modulation, whether an absolute value of the accumulated jitter J(t) reaches an equivalent of the clock period TCLK of the clock signal, and
- a circuit configured to drop a clock pulse effecting a compensation of the accumulated jitter equivalent to the clock period TCLK of the clock signal when the detector detects that the absolute value of the accumulated jitter J(t) reaches the equivalent of the clock period TCLK.
A system for frequency modulation of a clock signal, the system comprising:
- a modulator configured to modulate a frequency of the clock signal based on a predetermined modulation signal m(t);
- and
- a compensator configured to compensate an accumulated jitter J(t) caused by the frequency modulation of the clock signal by modification of the clock signal such that an absolute value of the accumulated jitter J(t) does not exceed a predetermined jitter limit Jlim, wherein the compensation comprises a reduction of the accumulated jitter caused by the frequency modulation and is independent of a further clock signal.
A method for reducing jitter caused by frequency modulation of a clock signal, comprising:
- modulating a frequency of the clock signal based on a predetermined modulation signal m(t);
- and
- compensating for an accumulated jitter J(t) caused by the frequency modulation of the clock signal such that an absolute value of the accumulated jitter J(t) does not exceed a predetermined jitter limit Jlim, wherein the frequency modulation of the clock signal and the compensation of the accumulated jitter J(t) are performed such that characteristics of the clock signal are substantially unchanged with respect to a corresponding clock signal without frequency modulation.
A method for jitter reduction comprising:
- subtracting a predetermined time varying clock period error signal t(t) from a clock period TCLK of a single clock source to cause an accumulated jitter J(t) of a corresponding clock signal over time, wherein the sign of t(t) is always the same and the sign of J(t) is always the same;
- detecting whether an absolute value of the accumulated jitter J(t) reaches an equivalent of the clock period TCLK;
- and
- modifying the clock signal effecting a predetermined phase shift of the clock signal corresponding to a predetermined jitter limit Jlim whenever the absolute value of the accumulated jitter J(t) reaches the predetermined jitter limit Jlim.
Dependencies are inferred from the claim text.