Dual port memory cell

A method of constructing a dual-port memory cell, comprising:

• forming a plurality of well regions in a substrate and extending in parallel in a first direction (y);
• on each of the plurality of well regions, forming a respective set of one or more fin structures, each fin structure extending in the first direction (y);
• forming a plurality of gate structures, each gate structure disposed over one or more of the sets of fin structures and extending in a second direction (x) that is perpendicular to the first direction (y), the sets of fin structures and gate structures configured and arranged to form FinFETs;
• and
• placing electrically conductive lines to couple the FinFETs to form a memory cell having:
• first and second inverter circuits, each inverter circuit including a pull-up transistor of a first type and a pull-down transistor of a second type;
• wherein in each inverter circuit, a gate of the pull-up transistor, and a gate of the pull-down transistor are each coupled to a first node and receive the same voltage potential;
• wherein a source of the pull-up transistor and a drain of the pull-down transistor are coupled in series and provide an inverted output at a second node between the pull-up and pull-down transistors;
• wherein the first node of each inverter circuit is coupled to the second node of the other inverter circuit to receive the inverted output of the other inverter circuit;
• a first pair of access transistors of the first type, each coupled to the first node of a respective one of the first and second inverter circuits;
• and
• a second pair of access transistors of the second type, each coupled to the first node of a respective one of the first and second inverter circuits.

A multi-port memory cell, comprising:

• first and second inverter circuits, each inverter circuit including a pull-up transistor of a first type and a pull-down transistor of a second type;
• wherein in each inverter circuit:
• a gate of the pull-up transistor and a gate of the pull-down transistor are each coupled to a first node and receive the same voltage potential;
• a source of the pull-up transistor and a drain of the pull-down transistor are coupled in series and provide an inverted output at a second node between the pull-up and pull-down transistors;
• and
• the first node of each inverter circuit is coupled to the second node of the other inverter circuit to receive the inverted output of the other inverter circuit;
• a first pair of access transistors of the first type, each coupled to the first node of a respective one of the first and second inverter circuits;
• and
• a second pair of access transistors of the second type, each coupled to the first node of a respective one of the first and second inverter circuits;
• wherein:
• the multi-port memory cell includes an even number (N) of pairs of access transistors, where N>2;
• and
• a total number of access transistors in the multi-port memory cell includes a first number (X) of p-type transistors, and a second number (Y) of n-type transistors, where X=Y.