Semiconductor device and semiconductor memory device

A semiconductor memory device comprising:

• a bit line sense amplification unit configured to sense and amplify data stored in a memory cell and transmit the amplified data to a first data line pair;
• a data transmission unit configured to transmit the data transmitted through the first data line pair to a second data line pair in response to a transmission control signal;
• an output sense amplification unit configured to sense and amplify the data transmitted through the second data line pair and output the amplified data to a data pad;
• and
• first and second power supply voltage generation units that separately generate precharging voltages to be applied to the first and second data line pairs, respectively, in response to a first precharging control signal and a second precharging control signal that controls a precharging operation regardless of an activation of an input/output control signal.