US 8,913,451 B2 · Memory device and test method thereof

Abstract

A method for testing a memory device includes entering a test mode in which multiple memory banks operate in a same manner, allowing a row corresponding to a row address in the multiple memory banks to be activated, latching a bank address and the row address corresponding to the multiple memory banks, writing same data in a column selected by a column address in the multiple memory banks, reading the data written in the writing of the data from the multiple memory banks, checking whether the data read from the multiple memory banks in the reading of the data are equal to each other, and programming the row address to locations designated by the bank address latched in the latching in a nonvolatile memory when the data read from the multiple memory banks are different from each other.

Claims18

Dependent claims

A method for testing a memory device, comprising:

entering a test mode in which two or more memory banks operate in a same manner;
allowing a row corresponding to a row address in the two or more memory banks to be activated;
latching a bank address and the row address corresponding to the two or more memory banks;
writing same data in a column selected by a column address in the two or more memory banks;
reading the data written in the writing of the data from the two or more memory banks;
checking whether the data read from the two or more memory banks in the reading of the data are equal to each other;
and
programming the row address to locations designated by the bank address latched in the latching in a nonvolatile memory when the data read from the two or more memory banks are different from each other.

5 more elements

A memory device comprising:

a plurality of memory banks configured to allow a row corresponding to a row address to be activated when bank activation signals corresponding to the plurality of memory banks are activated, and to perform read and write operations for a column corresponding to a column address when bank selection signals corresponding to the plurality of memory banks are activated;
a bank selection unit configured to generate the bank selection signals in response to a bank address, and to simultaneously activate two or more bank selection signals when a test mode is set;
a bank active control unit configured to generate the bank activation signals in response to an active command and the bank selection signals;
a plurality of input/output circuits configured to be provided to the corresponding memory banks, to be activated in response to the corresponding bank selection signal, to transfer write data to the corresponding memory banks in a write operation, and to output read data from the corresponding memory bank in a read operation;
a latch unit configured to latch the bank address and the row address when the active command is activated after the test mode is set;
a fail flag generation unit configured to compare read data transferred from the input/output circuits corresponding to the activated bank selection signals when the test mode is set, and to generate a fail flag based on the comparison result;
and
a nonvolatile memory configured to store the row address latched in the latch unit in a location designated by the bank address latched in the latch unit when the fail flag is activated.

5 more elements

A memory device comprising:

first to Nth bank groups (N is an integer equal to or more than 2), each of which including two or more memory banks configured to allow row corresponding to row address to be active when bank activation signals corresponding to the memory banks are activated, and to perform read and write operations for column corresponding to column address when bank selection signals corresponding to the memory banks are activated;
a bank selection unit configured to generate the bank selection signals in response to a bank address, and to activate the plurality of bank selection signals when a test mode is set;
a bank active control unit configured to generate the bank activation signals in response to an active command and the bank selection signals;
a plurality of input/output circuits configured to be provided to the corresponding memory banks, to be activated in response to the corresponding bank selection signals, to transfer write data to the corresponding memory banks in a write operation, and to output read data from the corresponding memory banks in a read operation;
a latch unit configured to latch the row address when the active command is activated after the test mode is set;
first to Nth fail flag generation units configured to correspond to the first to Nth bank groups in a one-to-one manner, compare read data transferred from the input/output circuits corresponding to the memory banks in the corresponding bank groups when the test mode is set, and to generate first to Nth fail flags based on the comparison result;
and
a nonvolatile memory configured to store the row address latched in the latch unit in a location designated by an activated fail flag of the first to Nth fail flags.

5 more elements

Dependencies are inferred from the claim text.

Memory device and test method thereof

Life of this patent

Memory device and test method thereof

Life of this patent

Abstract

Claims18