System and method of in-system repairs or configurations for memories

A memory, comprising:

• a plurality of normal memory cells and a plurality of redundant memory cells;
• at least one selector to select normal memory cells or redundant memory cells;
• at least one One-Time Programmable (OTP) memory having a plurality of OTP cells configured to store one or more defective addresses, the OTP cells can be programmed or read with at least one supply voltage no more than 4.0 Volts;
• and
• at least one match circuit configured to evaluate whether an access memory address has been stored as a defective address in the OTP memory,
• wherein the memory can be repaired or configured by programming new defective addresses or configuration parameters into the OTP memory,
• wherein the memory is provided in a memory package having a plurality of pins, including at least one Non-Connect (NC) pin, and wherein the OTP memory can be programmed by a program voltage supplied from at least one Non-Connect (NC) pin of the memory.

An electronic system, comprising:

• a processor;
• and
• a memory operatively connected to the processor, the memory comprising:
• a plurality of normal memory cells to provide data storage;
• a plurality of redundant memory cells for repair of one or more of the normal memory cells;
• at least one selector to select at least one of the normal memory cells or the redundant memory cells;
• at least one One-Time Programmable (OTP) memory having a plurality of OTP cells configured to store one or more defective addresses;
• and
• at least one comparison circuit configured to compare an access memory address with the one or more defective addresses stored in the OTP memory to produce a select signal used by the at least one selector to select at least one of the normal memory cells or the redundant memory cells,
• wherein the memory can be repaired or configured by programming defective addresses or new configuration parameters into the OTP memory.

A method for in-system repairing or configuring a memory, comprising:

• providing a plurality of normal memory cells and a plurality of redundant memory cells;
• providing at least a selector to select one or more of the normal cells or the redundant cells;
• storing at least one defective address in an OTP memory having a plurality of OTP cells configured to store defective addresses;
• and
• programming or reading at least one of the OTP cells in the OTP memory;
• and
• repairing the memory using the at least one defective address in the OTP memory to make use of at least one of the redundant memory cells, the repairing being achieved while the memory remains electronically and physically connected within an electronic system.

A memory, comprising:

• a plurality of normal memory cells and a plurality of redundant memory cells;
• at least one selector to select the normal memory cells or the redundant memory cells;
• at least one One-Time Programmable (OTP) memory having a plurality of OTP cells configured to store defective addresses;
• and
• wherein each of the OTP cells include at least one segment of interconnect as OTP element,
• wherein the memory can be configured or repaired by programming configuration parameters or defective address into the OTP memory while the memory being still electronically and physically connected within an electronic system.