Method and apparatus for memory command input and control

A memory, comprising:

• an interconnect bus;
• at least one master memory unit coupled to the interconnect bus and configured to receive a plurality of command signals representing a command and a plurality of chip select signals, the at least one master memory unit configured to provide the command and a chip enable signal to the interconnect bus responsive to receipt of the plurality of command signals and at least one of the a plurality of chip select signals being active and to not provide the command to the interconnect bus responsive to the plurality of chip select signals being inactive;
• and
• a slave memory unit coupled to the interconnect bus, the slave memory unit configured to be enabled and receive the command from the interconnect bus responsive to receipt of the chip enable signal.

A method for executing memory commands, comprising;

• receiving at a master memory unit a plurality of command signals and a plurality of chip select signals, each of the plurality of chip select signals having an active state or an inactive state;
• decoding the plurality of command signals at a master memory unit;
• outputting a command to an interconnect bus responsive, at least in part, to receipt of at least one active chip select signal, the command having a first width;
• and
• outputting at least one chip enable signal to the interconnect bus responsive to decoding a valid command, the at least one chip enable signal having a second width less than the first width.

A method for executing memory commands, comprising:

• receiving an active chip select signal at a master memory unit;
• generating a memory command responsive to receipt of an active chip select signal;
• outputting the memory command to an interconnect bus;
• executing the command at a slave memory unit;
• receiving an inactive chip select signal at a master memory unit;
• and
• not providing a memory command to the interconnect bus responsive to receipt of the inactive chip select signal.

A memory comprising:

• a memory unit of a first type configured to receive chip select signals, the memory unit of a first type farther configured to output a command and at least one enable signal responsive, at least in part, to at least one chip select signal being active, wherein the memory unit of a fist type is further configured to truncate the at least one enable signal;
• and
• a plurality of memory units of a second type coupled to the memory unit of a first type and configured to receive the command and the at least one enable signal, a memory unit of a second type of the plurality of memory units of a second type further configured to execute the command responsive to the at least one enable signal corresponding to the memory unit of a second type of the plurality of memory units of a second type;
• wherein the memory unit of a first type and the plurality of memory units of a second type are arranged in a stack.