Nonvolatile semiconductor memory device

The nonvolatile semiconductor memory device comprising:

• a memory cell array including a plurality of memory cells arranged in a matrix;
• and
• a write control unit configured to control a write operation for the memory cells and configured to control a write verify operation on the basis of a target verify level of a threshold distribution,
• wherein the write control unit performs a first write operation with respect to a first threshold distribution, a first verify operation with respect to the first threshold distribution, and a second write operation on the basis of a result of the first verify operation, and starts a third write operation with respect to a second threshold distribution,
• wherein the memory cell array includes:
• a NAND string including the memory cells connected in series;
• a first select transistor connected to one end of the NAND string;
• and
• a second select transistor connected to another end of the NAND string.

A nonvolatile semiconductor memory device comprising:

• a memory cell array including a plurality of memory cells arranged in a matrix;
• and
• a write control unit configured to control a write operation for the memory cells and configured to control a write verify operation on the basis of a target verify level of a threshold distribution,
• wherein the write control unit performs:
• a first write operation with respect to a first threshold distribution;
• a second write operation with respect to at least one second threshold distribution except for the first threshold distribution;
• a first verify operation for the first threshold distribution and the second threshold distribution;
• a third write operation with respect to the first threshold distribution on the basis of a result of the first verify operation;
• and
• a fourth write operation with respect to the second threshold distribution on the basis of the result of the first verify operation.

A nonvolatile semiconductor memory device comprising:

• a memory cell array including a plurality of memory cells arranged in a matrix;
• and
• a control circuit configured to control a write operation for the memory cells and configured to control a write verify operation on the basis of a target verify level of a threshold distribution,
• wherein the control circuit searches for a low-level area and a high-level area of the threshold distribution by performing a search verify operation on the basis of a write verify level smaller than the target verify level, and shifts the low-level area toward a high-level side by performing a rewrite operation only in one or more of the memory cells belonging to the low-level area.