Method and apparatus for adjusting drain bias of a memory cell with addressed and neighbor bits

#Charge trapping memory cells such as NROM can be programmed at different localized parts of the silicon nitride storage layer by a mechanism such as channel hot electron (CHE) injection. A single memory cell can store differently addressed data at different parts of the nitride storage layer, proximate to the source and proximate to drain. Threshold voltage ranges of memory cells are associated with the different possible data values that can be stored in each part of the memory cell. For example, in each part of a multi-level cell, 4 threshold voltage ranges can represent 4 distinct data values to store 2 bits. In a triple-level cell, 8 threshold voltage ranges can represent 8 distinct data values to store 3 bits.

#However, because of the second bit effect, which limits the available threshold voltage window of a memory cell, the data stored at different parts of the nitride storage layer affect each other. The different parts are referred to here as the “addressed bit” and the “neighbor bit” of the same memory cell. In this context “bit” does not limit data storage to a single bit of data, and instead refers to different physical locations of the charge storage layer which can each store 1, 2, 3, or more bits of data. The addressed bit is the physical data location which is addressed in a command such as program or read, and the neighbor bit is the adjacent physical data location in the same memory cell as the addressed bit. The second bit effect is described next.

#When reading an addressed part of the memory cell, a reverse read operation is performed as described in U.S. Pat. No. 6,011,725, incorporated by reference, in which the polarity of voltages applied to the source and drain is reversed from the CHE programming operation performed on the addressed part of the memory cell. The reverse read operation performed on the addressed part of the memory cell must “punch through” the channel located under the neighbor bit of the same memory cell. When the neighbor bit of the memory cell stores a data value associated with a high threshold voltage, then the reverse read current is reduced. This is the second bit effect which effectively narrows the available threshold voltage window, as described in “Studies of the reverse read method and second-bit effect of 2-bit/cell nitride-trapping device by quasi-two-dimensional model” by Hang-Ting Lue et al., IEEE Transactions on Electron Devices, VOl. 43, No. 1, page 119, January 2006, incorporated by reference.

#FIGS. 1-2 are diagrams of a nonvolatile memory cell with an addressed bit and a neighboring bit that store separately addressed data.

#FIGS. 3-5 are threshold voltage diagrams showing the second bit effect of a neighboring bit on an addressed bit.

#FIGS. 6-7 are threshold voltage diagrams of an increased drain voltage that reduces the second bit effect of a neighboring bit on an addressed bit.

#The shown examples have four possible data values in a memory cell. Other examples can have two possible data values, eight possible data values, or some other possible number of data values.

#FIGS. 1-2 are diagrams of a nonvolatile memory cell with an addressed bit and a neighboring bit that store separately addressed data.

#FIG. 1 shows a nonvolatile memory cell with data stored at different parts of the nitride storage layer. The different parts are referred to here as the “addressed bit” and the “neighbor bit” of the same memory cell. In this context “bit” refers to different physical locations of the charge storage layer which can each store 1, 2, 3, or more bits of data. The memory cell has a gate terminal, and two current carrying terminals—the source and drain terminals. The drain terminal voltage is varied with the data value proximate to the source terminal. The particular current carrying terminal which is the drain terminal varies, because the particular current carrying terminal which acts as the sink for electron flow varies. In FIG. 1, the addressed bit is at the left part of the charge storage layer of the memory cell and proximate to the left current carrying terminal, and the neighbor bit is at the right part of the charge storage layer of the memory cell and proximate to the right current carrying terminal. The designation of the right and left current carrying terminals as the lower voltage source and the higher voltage drain, and the direction of electron flow to the drain, are shown for the different permutations of program and reverse read, and addressed bit and neighbor bit.