Enhanced glitch filter
AssigneeSanDisk Technologies LLC
InventorLeonid Minz
Life of this patent
Estimating the term…
Abstract
A glitch circuit includes an SR flip-flop where a received input clock is operatively coupled to set and reset inputs of the flip-flop, respectively. A configurable delay circuit receives an input signal, and an output of the delay circuit provides a delayed signal. The configurable delay circuit includes a plurality of switchable taps, each providing an increment of delay to the input signal. The delay circuit input is operatively coupled to an output of the flip flop, and an output of the delay circuit is operatively coupled to the inputs of the flip-flop. The glitch circuit captures a first signal transition of the input clock and blocks all other transitions from propagating through the flip-flop during a selected delay period so as to provide on an output of the flip-flop, the glitch-free output clock.
Claims23
A glitch circuit for filtering glitches from a received input clock, the glitch circuit comprising:
- an SR flip-flop having a set input, a reset input, and an output, wherein the received input clock is operatively coupled to the set and reset inputs of the flip-flop, respectively;
- a configurable delay circuit having a delay circuit input configured to receive an input signal, and having a delay circuit output configured to provide a delayed signal;
- the configurable delay circuit having a plurality of switchable taps, each tap configured to provide an increment of delay to the input signal so as to delay the input signal by a selected delay period;
- the delay circuit input operatively coupled to an output of the flip-flop, and the delay circuit output operatively coupled to the inputs of the flip-flop;
- and
- wherein the glitch circuit captures a first signal transition of the input clock and blocks all other signal transitions from propagating through the flip-flop during the selected delay period so as to provide a glitch-free output clock at the output of the flip-flop.
A memory device, comprising:
- a controller;
- a non-volatile flash memory circuit operatively coupled to the controller;
- glitch circuit operatively coupled to the controller and configured to receive an input clock;
- and
- the glitch circuit comprising:
- an SR flip-flop having a set input, a reset input, and an output, wherein the received input clock is operatively coupled to the set and reset inputs of the flip-flop, respectively;
- a configurable delay circuit having an delay circuit input configured to receive an input signal, and having a delay circuit output configured to provide a delayed signal;
- the configurable delay circuit having a plurality of switchable taps, each tap configured to provide an increment of delay to the input signal so as to delay the input signal by a selected delay period;
- the delay circuit input operatively coupled to an output of the flip-flop, and the delay circuit output operatively coupled to the inputs of the flip-flop;
- and
- wherein the glitch circuit captures a first signal transition of the input clock and blocks all other signal transitions from propagating through the flip-flop during the selected delay period so as to provide a glitch-free output clock on an output of the flip-flop.
A method for filtering glitches from a received input clock, the method comprising:
- providing an SR flip-flop having a set input, a reset input, and an output, and operatively coupling the received input clock to the set and reset inputs of the flip-flop, respectively;
- providing a configurable delay circuit having a delay circuit input configured to receive an input signal, and having a delay circuit output configured to provide a delayed signal;
- providing the configurable delay circuit with a plurality of switchable taps, each tap configured to provide an increment of delay to the input signal so as to delay the input signal by a selected delay period;
- operatively coupling the delay circuit input to an output of the flip-flop, and operatively coupling the delay circuit output to the inputs of the flip-flop;
- and
- capturing, a first signal transition of the input clock and blocking all other signal transitions from propagating through the flip-flop during the selected delay period so as to provide a glitch-free output clock at the output of the flip-flop.
Dependencies are inferred from the claim text.