Tracking mechanisms
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsDerek C. Tao, Annie-Li-Keow Lum, Yukit Tang, Kuoyuan (Peter) Hsu
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsDerek C. Tao, Annie-Li-Keow Lum, Yukit Tang, Kuoyuan (Peter) Hsu
Estimating the term…
A tracking edge of a tracking signal is activated. A buffer is turned off and a latching circuit is turned on, based on the tracking edge of the tracking signal. A buffer output of the buffer is coupled to a latch output of the latching circuit at a node. The buffer receives a data line of a memory macro.
A method comprising:
A tracking circuit comprising:
A circuit comprising:
Dependencies are inferred from the claim text.
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Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management: clock generating, synchronizing or…
Arrangements for writing information into, or reading information out from, a digital store: input/output [I/O] data interface arrangements, e.g.…
For memory cells of the field-effect type: read-write [R-W] circuits
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data output circuits, e.g. read-out amplifiers,…
About 6 years 5 months of term left · ends 31 Mar 2033 (estimated)
The present disclosure is related to tracking mechanisms.
Tracking circuits in a memory macro have tracking cells used to generate tracking or reference signals based on which signals for reading memory cells are generated. In an approach, one tracking circuit is used for memory cells in more than one segment of a memory macro. However, various circuitries such as the global clock, the X-address decoder, the global bit line, etc. of various segments may not be part of the tracking process.
In many approaches, tracking paths of the tracking circuits are in one direction, such as the X-decoder direction. Other directions are not tracked.
The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description, drawings, and claims.
FIG. 1A is a block diagram of a memory macro, in accordance with some embodiments.
FIG. 1B is a diagram of a memory segment, in accordance with some embodiments.
Like reference symbols in the various drawings indicate like elements.
Embodiments, or examples, illustrated in the drawings are disclosed below using specific language. It will nevertheless be understood that the embodiments and examples are not intended to be limiting. Any alterations and modifications in the disclosed embodiments, and any further applications of the principles disclosed in this document are contemplated as would normally occur to one of ordinary skill in the pertinent art.
Some embodiments have one or a combination of the following features and/or advantages. The active tracking bit lines and tracking cells in the X-decoder direction are in the same segment as the memory cell to be read (the accessed memory cell). As a result, the timings generated by the tracking cells are closer to the timings of the accessed memory cell. In other words, the variations between the tracking cells and the accessed cells are reduced. The resistance and capacitance of the global clock in the X-address decoders, the global bit lines, and the read word lines are part of the tracking process. As a result, the memory macro can operate with higher speeds over a large voltage range.