Memory device and corresponding reading method

#The present invention relates to the field of solid-state memory devices. In particular, the invention relates to non-volatile electrically erasable and programmable memory devices. In greater detail, the present invention relates to flash memory devices.

#The non-volatile electrically erasable and programmable memory devices—also identified by the acronym EEPROM, “Electrically Erasable Programmable Read Only Memory”—have reached a widespread use in the electronic applications market (from the industrial to the consumer level). Such a wide use is due to special features, such as the ability of retaining information without power supply, allowing the editing of the information thereof, and providing greater reliability than other storage devices, such as magnetic disk storage devices.

#The flash memory devices are, currently, the most widespread type of EEPROM devices in that, besides the features above mentioned, they have a very high storage capacity and present at the same time very reduced dimensions.

#Embodiments of the invention, as well as additional features and their advantages will be better understood with reference to the following detailed description, given merely by way of non-limiting example, to be read in conjunction with the attached figures (wherein corresponding elements are designated with the same or similar references and their explanation is not repeated for brevity). In this regard, it is expressly understood that the figures are not necessarily to scale (with some details that may be exaggerated and/or simplified) and, unless otherwise stated, they are simply used to conceptually illustrate the structures and procedures. In particular:

#FIG. 1 illustrates a principle block diagram of a portion of a flash memory according to an implementation known in the art;

#FIG. 2 shows a principle circuit diagram of a sense amplifier included in the circuit of FIG. 1 according to a known in the art implementation;

#With reference to FIG. 1, a block diagram of a portion of a flash memory 100, according to an implementation known in the art, is shown. More specifically, the flash memory 100 includes a matrix 105 of memory cells 110 arranged in rows and columns. The columns of the matrix 105 are divided in a number n (e.g. n=128) of blocks of data 112i (i=0, . . ., n−1) divided into clusters 115j (e.g. j=0, 1), each of which includes a predetermined number q of columns (e.g. q=8) of memory cells 110 adjacent to each other. Each memory cell 110 typically includes an N-channel MOS transistor with floating gate structure. For example, a typical flash memory of this type may comprise 2048 columns, organized in 128 blocks of data of 16 columns, each divided into two clusters of 8 columns.

#The memory cell 110 is adapted to store a binary data (bit) in the form of electric charge stored in the floating gate, which defines a corresponding value of the threshold voltage of the transistor. The memory cell 110 may be programmed to a high threshold voltage (electrical charges trapped in floating gate) to store a bit corresponding to a first logical value (e.g. a low logic value “0”) by applying a high programming voltage (e.g. 8-10V) to the gate terminal. In contrast, the memory cell 110 is erased to a low threshold voltage (floating gate deprived of electric charge) to store a bit corresponding to a second logical value (e.g. a high logic value “1”) by applying a high erasure difference potential (e.g. 10-15V) between the source and gate terminals. To read a bit a reading voltage (e.g. 4V) is applied to the gate terminal and the presence or absence of a current flow between source and drain terminals of the transistor is detected.

#Each row of the matrix 105 is associated with a respective row line (word line), while each column is associated with a respective column line (bit line). The memory 100 has a NOR architecture, according to which memory cells 110 of a same column are connected, through the drain terminals, in parallel to the bit line corresponding to that column.