US 8,913,436 B2 · Non-volatile memory (NVM) with word line driver/decoder using a charge pump voltage

Abstract

A word line driver that includes a pull up transistor for biasing a node of a stack of transistors that are located between a high supply voltage terminal and a low supply voltage terminal. The node is biased at a voltage that is between the high supply voltage and the low supply voltage. The stack of transistors includes a stack of decode transistors and a cascode transistor. The cascode transistor is located between the node and a second node of the stack that is coupled to an inverting circuit.

Drawings

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Drawings

Claims20

Dependent claims

A word line driver comprising:

a first stack of transistors, the first stack including:
a plurality of decode transistors coupled in a stack between a first node of the first stack of transistors and a first voltage supply terminal for supplying a first supply voltage, wherein each of the decode transistors includes a control electrode to receive a decode signal of a plurality of decode signals;
a cascode transistor having a first current electrode connected to the first node, the cascode transistor including a control electrode coupled to a source voltage terminal for providing a source voltage;
a third transistor, a first current electrode of the third transistor is connected to a second node of the first stack of transistors, wherein the second current electrode of the third transistor is coupled to a second supply voltage terminal for supplying a second supply voltage, the second node is coupled to a second current electrode of the cascode transistor;
a pull up transistor having a first current electrode coupled to the first node, a second current electrode coupled to a third supply voltage terminal for supplying a third supply voltage, and a control electrode coupled to a decode signal of the plurality of decode signals, wherein the second supply voltage is higher than the first supply voltage and higher than the third supply voltage, wherein the third supply voltage is higher than the first supply voltage;
and
an inverting circuit including an input and an output, the input is coupled to the second node, wherein inverting circuit provides at its output, and inverted logic state of the second node;
wherein the plurality of decode transistors are characterized as lower voltage transistors;
and
wherein the third transistor is characterized as a higher voltage transistor.

7 more elements

A word line driver comprising:

a first stack of transistors, the first stack including:
a plurality of decode transistors coupled in a stack between a first node of the first stack of transistors and a first voltage supply terminal for supplying a first supply voltage, wherein each of the decode transistors includes a control electrode to receive a decode signal of a plurality of decode signals;
a first cascode transistor having a first current electrode connected to the first node, the first cascode transistor including a control electrode coupled to a source voltage terminal for providing a source voltage;
a second cascode transistor having a first current electrode coupled to a second current electrode of the first cascode transistor;
and
a third transistor, a first current electrode of the third transistor is connected to a second node of the first stack of transistors, wherein the second current electrode of the third transistor is coupled to a second supply voltage terminal for supplying a second supply voltage, the second node is coupled to a second current electrode of the second cascode transistor;
a pull up transistor having a first current electrode connected to the first node, a second current electrode coupled to a third supply voltage terminal for supplying a third supply voltage, and a control electrode connected to a decode signal of the plurality of decode signals, wherein the second supply voltage is higher than the first supply voltage and higher than the third supply voltage, wherein the third supply voltage is higher than the first supply voltage;
and
an inverting circuit including an input and an output, the input is coupled to the second node, wherein inverting circuit provides at its output, and inverted logic state of the second node;
wherein the plurality of decode transistors, the first cascode transistor, and the pull up transistor are characterized as lower voltage transistors;
wherein the third transistor and the second cascode transistor are characterized as higher voltage transistors;
and
wherein the plurality of decode transistors, the first cascode transistor, and the second cascode transistor are N-channel transistors, and the pull up transistor and the third transistor are P-channel transistors.

10 more elements

Dependencies are inferred from the claim text.

Description4,503 words

Summary225 words

#1. Field

#This disclosure relates generally to non-volatile memories (NVM), and more specifically, to NVMs that use a charge pump voltage in a word line driver/decoder.

#2. Related Art

Brief description of the drawings3 figures

#The present disclosure is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

#FIG. 1 is a block diagram of an embodiment of a non-volatile memory (NVM) in accordance with the present disclosure;

#FIG. 2 is a circuit diagram of a word line driver/decoder of the NVM of FIG. 1; and

Detailed description4,183 words

#In one aspect a word line driver/decoder of a non-volatile memory (NVM) has a series decoder of N channel transistors between a select node and ground in which the select node is brought to a logic low by the N channel transistors all being conductive. Between a charge pump voltage and the select node is a conductive load that is prevented from being a leakage path from the charge pump voltage through the N channel transistors by applying a reference voltage, which may be an external power supply voltage, to the select node. This is better understood by reference to the drawings and the following description.

#VB1 is a voltage that limits the amount of current that P channel 32 may conduct to ensure that transistors 38-42 can pull nodes 35 and 39 to a logic low. VB2 is a voltage that makes sure that devices below transistor 34 receive a voltage no greater than a safe voltage for low voltage transistors which means VB2 equals VDD plus a threshold voltage of transistor 34.

#Shown in FIG. 1 is a block diagram of a non-volatile memory (NVM) comprising a row pre-decoder 12 that receives a row address, a word line driver/decoder 14 coupled to the row pre-decoder and a word line WL0, a word line driver/decoder 16 coupled to row predecoder 12 and a word line WL1, a memory controller 18 coupled to row predecoder 12 and word line driver/decoders 14 and 16 that has an input/output shown as I/O, a charge pump 19 that is within memory controller 18, column circuitry 20 coupled to memory controller 18 and that receives a column address, and an array 22 coupled to column circuitry 20 and word line driver/decoders 14 and 16 through word lines WL0 and WL1, respectively.

Facts

Application

13/826,958Filed 14 Mar 2013

Published

US 2014/0269140 A118 Sep 2014

Granted

16 Dec 2014

Term ends

14 Mar 2033

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification3 codes

G11C 8/08
Arrangements for selecting an address in a digital store: word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down…
G11C 16/08
Auxiliary circuits, e.g. for writing into memory: address circuits; Decoders; Word-line control circuits
G11C
Static stores

Timeline

14 Mar 2013Application filedUS 13/826,958
14 Mar 2013Assigned to Freescale Semiconductor, Inc.assignment of assignor's interest
20 May 2013Assigned to Citibank, N.A., AS Notes Collateral Agentsupplement to ip security agreement
20 May 2013Assigned to Citibank, N.A., AS Notes Collateral Agentsupplement to ip security agreement
20 May 2013Assigned to Citibank, N.A., AS Collateral Agentsupplement to ip security agreement
18 Jun 2013Assigned to Citibank, N.A., AS Notes Collateral Agentsecurity agreement
6 Nov 2013Assigned to Citibank, N.A., AS Notes Collateral Agentsecurity agreement
18 Sep 2014PublishedUS 2014/0269140 A1
16 Dec 2014GrantedUS 8,913,436 B2
21 Dec 2015Assigned to Freescale Semiconductor, Inc.patent release
21 Dec 2015Assigned to Freescale Semiconductor, Inc.patent release
21 Dec 2015Assigned to Freescale Semiconductor, Inc.patent release
12 Jan 2016Assigned to Morgan Stanley Senior Funding, Inc.assignment and assumption of security interest in patents
13 Jan 2016Assigned to Morgan Stanley Senior Funding, Inc.assignment and assumption of security interest in patents
16 Jun 2016Assigned to Morgan Stanley Senior Funding, Inc.supplement to the security agreement
21 Sep 2016Assigned to NXP, B.V., F/K/A Freescale Semiconductor, Inc.release of security interest
7 Nov 2016Assigned to NXP B.V.release of security interest
3 Jan 2017Assigned to NXP USA, Inc.merger
1 Feb 2017Assigned to Morgan Stanley Senior Funding, Inc.corrective assignment to correct the remove patents 8108266 and 8062324 and replace them with 6108266 and 8060324 previously recorded on reel 037518 frame 0292. assignor(s) hereby confirms the assignment and assumption of security interest in patents.
20 Feb 2019Assigned to Shenzhen Xinguodu Technology Co., Ltd.corrective assignment to correct the to correct the application no. from 13,883,290 to 13,833,290 previously recorded on reel 041703 frame 0536. assignor(s) hereby confirms the the assignment and assumption of security interest in patents..
10 Sep 2019Assigned to NXP B.V.release of security interest
10 Dec 2019Assigned to Morgan Stanley Senior Funding, Inc.corrective assignment to correct the remove application 11759915 and replace it with application 11759935 previously recorded on reel 037486 frame 0517. assignor(s) hereby confirms the assignment and assumption of security interest in patents.
17 Jan 2020Assigned to NXP B.V.corrective assignment to correct the remove application 11759915 and replace it with application 11759935 previously recorded on reel 040928 frame 0001. assignor(s) hereby confirms the release of security interest.
17 Feb 2020Assigned to NXP, B.V. F/K/A Freescale Semiconductor, Inc.corrective assignment to correct the remove application 11759915 and replace it with application 11759935 previously recorded on reel 040925 frame 0001. assignor(s) hereby confirms the release of security interest.
12 Oct 2026TodayWithin its term
14 Mar 2033Term endsEstimated

Non-volatile memory (NVM) with word line driver/decoder using a charge pump voltage

Life of this patent

Non-volatile memory (NVM) with word line driver/decoder using a charge pump voltage

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims20

Description4,503 words

Drawings

Classification3 codes

Life of this patent

Description4,503 words