Programming select gate transistors and memory cells using dynamic verify level

A non-volatile storage system, comprising:

• a substrate;
• a set of transistors which are to be programmed in a programming operation, the set of transistors is in a memory device, the memory device comprises a plurality of memory cells formed above a substrate in multiple physical levels of memory cells in a three-dimensional non-volatile memory, the plurality of memory cells comprise columnar active areas;
• and
• circuitry coupled with the set of transistors, the circuitry:
• performs each program-verify iteration of a plurality of program-verify iterations of the programming operation for the set of transistors, each transistor initially has a program status which indicates that the transistor is to be programmed, each program-verify iteration involves application of a program pulse to the set of transistors, a determination of whether a threshold voltage of at least some of the transistors with the program status exceeds a lockout verify voltage and a change of the program status to a lockout status for a remainder of the programming operation for each of the transistors for which the threshold voltage is determined to exceed the lockout verify voltage, the lockout verify voltage is stepped up in multiple program-verify iterations of the program-verify iterations for the set of transistors.

A method for programming memory cells, comprising:

• performing each program-verify iteration of a plurality of program-verify iterations, the plurality of program-verify iterations comprise program-verify iterations for one set of memory cells which are to be programmed to one target data state using a lockout verify voltage of the one target data state in a programming operation, and program-verify iterations for another set of memory cells which are to be programmed to another target data state using a lockout verify voltage of the another target data state in the programming operation, each memory cell in the one set of memory cells and the another set of memory cells initially has a program status which indicates that the memory cell is to be programmed, the one set of memory cells and the another set of memory cells comprise columnar active areas and are formed above a substrate in multiple physical levels of memory cells in a three-dimensional non-volatile memory, the performing each program-verify iteration comprises:
• applying a program pulse to the one set of memory cells and the another set of memory cells;
• determining whether a threshold voltage of at least some of the memory cells in the one set of memory cells with the program status exceeds the lockout verify voltage of the one target data state and changing the program status to a lockout status for a remainder of the programming operation for each of the memory cells in the one set of memory cells for which the threshold voltage is determined to exceed the lockout verify voltage of the one target data state;
• and
• determining whether a threshold voltage of at least some of the memory cells in the another set of memory cells with the program status exceeds the lockout verify voltage of the another target data state and changing the program status to the lockout status for a remainder of the programming operation for each of the memory cells in the another set of memory cells for which the threshold voltage is determined to exceed the lockout verify voltage of the another target data state, the lockout verify voltage of the one target data state is stepped up in the program-verify iterations for the one set of memory cells at a different rate than a rate at which the lockout verify voltage of the another target data state is stepped up in the program-verify iterations for the another set of memory cells.