Pseudo block operation mode in 3D NAND
AssigneeSanDisk Technologies LLC
InventorsXiying Costa, Alexander Kwok-Tung Mak, Chris Avila, Gautam Dusija, Man Mui
Life of this patent
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Abstract
A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each group of the different groups comprises multiple adjacent storage elements of the plurality of storage elements; and a control circuit in communication with the string, the control circuit, to perform a Pseudo Block Operation Mode.
Claims38
A three-dimensional stacked non-volatile memory device, comprising:
- a substrate;
- a plurality of sets of memory cells above the substrate in multiple physical levels, each set of memory cells comprising an active area comprising a channel that extends vertically through the physical levels, the sets of memory cells are associated with pseudo blocks, each pseudo block comprises a portion of each of the sets of memory cells, each of the sets of memory cells is a member of each of the pseudo blocks, wherein each of the memory cells is characterized by a memory hole size, the memory cells are associated with pseudo blocks based on memory hole size;
- and
- circuitry associated with operation of the plurality of sets of memory cells, the circuitry is in communication with the plurality of sets of memory cells, the circuitry operates in a pseudo block operation mode that performs operations associated with the plurality of sets of memory cells on a pseudo block level for the three-dimensional stacked non-volatile memory device.
A method of operating a three-dimensional stacked non-volatile memory device comprising a plurality of sets of memory cells above a substrate in multiple physical levels and circuitry associated with operation of the plurality of sets of memory cells, each set of memory cells comprising an active area comprising a channel that extends vertically through the physical levels, the method comprising:
- subdividing the memory cells into pseudo blocks based on a programming speed of the respective memory cells, the pseudo blocks each comprise a portion of each of the sets of memory cells, each of the sets of memory cells is a member of each of the pseudo blocks;
- and
- performing, by the circuitry, operations associated with the plurality of sets of memory cells on a pseudo block level for the three-dimensional stacked non-volatile memory device.
A three-dimensional stacked non-volatile memory device, comprising:
- a substrate;
- a plurality of sets of memory cells above the substrate in multiple physical levels, each set of memory cells comprising an active area comprising a channel that extends vertically through the physical levels, wherein the sets of memory cells are associated with pseudo blocks that each comprise a portion of each of the sets of memory cells, wherein each of the sets of memory cells is a member of each of the pseudo blocks;
- and
- circuitry associated with operation of the plurality of sets of memory cells, wherein the circuitry is configured to record access times to read the memory cells in respective pseudo blocks, the circuitry is further configured to determine whether the access time for each respective pseudo block exceeds a limit for the respective pseudo block.
A method of operating a three-dimensional stacked non-volatile memory device comprising a plurality of sets of memory cells above a substrate in multiple physical levels, each set of memory cells comprising an active area comprising a channel that extends vertically through the physical levels, the plurality of sets of memory cells are associated with pseudo blocks, the pseudo blocks each comprise a portion of each of the sets of memory cells, each of the sets of memory cells is a member of each of the pseudo blocks, the method comprising:
- for each of the respective pseudo blocks, recording a number of reads of the respective pseudo block;
- and
- determining whether the number of reads for each respective pseudo block exceeds a limit for the respective pseudo block, wherein at least two of the pseudo blocks have a different limit for the number of reads.
A three-dimensional stacked non-volatile memory device, comprising:
- a substrate;
- a plurality of sets of memory cells above the substrate in multiple physical levels, each set of memory cells comprising an active area comprising a channel that extends vertically through the physical levels, wherein the sets of memory cells are associated with pseudo blocks that each comprise a portion of each of the sets of memory cells, wherein each of the sets of memory cells is a member of each of the pseudo blocks;
- and
- circuitry associated with operation of the plurality of sets of memory cells, wherein the circuitry is configured to record the number of program/erase cycles for each respective pseudo block, the circuitry is further configured to determine whether the number of program/erase cycles for each respective pseudo block exceeds a limit for the respective pseudo block.
A method of operating a three-dimensional stacked non-volatile memory device comprising a plurality of sets of memory cells above a substrate in multiple physical levels, each set of memory cells comprising an active area comprising a channel that extends vertically through the physical levels, the plurality of sets of memory cells are associated with pseudo blocks, the pseudo blocks each comprise a portion of each of the sets of memory cells, each of the sets of memory cells is a member of each of the pseudo blocks, the method comprising:
- for each of the respective pseudo blocks, recording the number of program/erase cycles for the respective pseudo block;
- and
- determining whether the number of program/erase cycles for each respective pseudo block exceeds a limit for the respective pseudo block, wherein at least two of the pseudo blocks have a different limit for the program/erase cycles.
A three-dimensional stacked non-volatile memory device, comprising:
- a substrate;
- a plurality of sets of memory cells above the substrate in multiple physical levels, each set of memory cells comprising an active area comprising a channel that extends vertically through the physical levels;
- and
- circuitry associated with operation of the plurality of sets of memory cells, the circuitry is configured to subdivide the memory cells into pseudo blocks based on a programming speed of the respective memory cells, the pseudo blocks each comprise a portion of each of the sets of memory cells, each of the sets of memory cells is a member of each of the pseudo blocks, the circuitry is further configured to operate in a pseudo block operation mode that performs operations associated with the plurality of sets of memory cells on a pseudo block level for the three-dimensional stacked non-volatile memory device.
A method of operating a three-dimensional stacked non-volatile memory device comprising a plurality of sets of memory cells above a substrate in multiple physical levels and circuitry associated with operation of the plurality of sets of memory cells, each set of memory cells comprising an active area comprising a channel that extends vertically through the physical levels, the plurality of sets of memory cells are associated with pseudo blocks, the pseudo blocks each comprise a portion of each of the sets of memory cells, each of the sets of memory cells is a member of each of the pseudo blocks, wherein each of the memory cells is characterized by a memory hole size, the memory cells are associated with pseudo blocks based on memory hole size, the method comprising:
- performing, by the circuitry, operations associated with the plurality of sets of memory cells on a pseudo block level for the three-dimensional stacked non-volatile memory device.
Dependencies are inferred from the claim text.