US 8,913,426 B2Granted

Read distribution management for phase change memory

AssigneeMicron Technology, Inc.

InventorsFerdinando Bedeschi, Roberto Gastaldi

Life of this patent

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Abstract

Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.

Drawings

Claims22

Dependent claims

A method of reading a memory cell in a memory array, comprising:

providing a reference cell current delta for each of a plurality of current steps corresponding to a memory state of the memory cell, wherein the reference cell current delta is determined by comparing a current of a reference cell in the memory array at a point in time to a current of the reference cell at an earlier point in time;
and
determining the state of the memory cell based at least in part on a comparison between a memory cell current of the memory cell and a read reference current, the comparison being adjusted by the reference cell current delta associated with an applied current step.

Dependencies are inferred from the claim text.

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US 8,913,426 B2Granted

Read distribution management for phase change memory

AssigneeMicron Technology, Inc.

InventorsFerdinando Bedeschi, Roberto Gastaldi

Life of this patent

About 4 years of term left · ends 15 Oct 2030 (estimated)

Priority15 Oct 2010

Filed10 Jun 2013

Granted16 Dec 2014

Today12 Oct 2026

Term ends15 Oct 2030

Priority15 Oct 2010

Granted16 Dec 2014

Term ends15 Oct 2030

Life of this patent

Estimating the term…

Abstract

Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.

Drawings

Drawings are temporarily unavailable. Open the PDF at USPTO

Drawings

Claims22

Dependent claims

A method of reading a memory cell in a memory array, comprising:

providing a reference cell current delta for each of a plurality of current steps corresponding to a memory state of the memory cell, wherein the reference cell current delta is determined by comparing a current of a reference cell in the memory array at a point in time to a current of the reference cell at an earlier point in time;
and
determining the state of the memory cell based at least in part on a comparison between a memory cell current of the memory cell and a read reference current, the comparison being adjusted by the reference cell current delta associated with an applied current step.

Dependencies are inferred from the claim text.

Description5,507 words

Summary247 words

#1. Field

#Subject matter disclosed herein relates to a memory device, and more particularly to read/write performance of phase change memory.

#2. Information

Brief description of the drawings8 figures

#Non-limiting and non-exhaustive embodiments will be described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various figures unless otherwise specified.

#FIG. 1 is a plot of characteristics of bias signal waveforms, according to an embodiment.

#FIG. 2 is a plot showing a distribution of states of memory cells in a PCM, according to an embodiment.

Detailed description5,097 words

#Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of claimed subject matter. Thus, the appearances of the phrase “in one embodiment” or “an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in one or more embodiments.

#Embodiments described herein include processes and/or electronic architecture involving managing read distributions for single-level cell (SLC) or multi-level cell (MLC) phase change memory (PCM) devices. Managing read distributions of PCM cells may be used to avoid read errors in response to a shift in a state distribution of the PCM cells that may occur over time, as described below. A state distribution of a memory cell, for example, may correspond to one or more threshold voltages corresponding to a number of states or logic levels stored by the memory cell. In other words, such states or logic levels may correspond to voltage ranges separated by threshold voltages. For example, a first logic level may correspond to a first voltage range, a second logic level may correspond to a second voltage range, a third logic level may correspond to a third voltage range, and so on. Individual logic levels may correspond to two-bit data, such as “00” for a first logic level, “01” for a second logic level, “10” for a third logic level, and “11” for a fourth logic level, for example.

#In an embodiment, a method of reading a memory cell programmed at a particular current may include compensating for a change in the particular current. Such a change, for example, may result from changes in various physical phenomena, such as resistivity drift of PCM material, temperature changes, retention, and so on, as described in detail below. Such a change in current may occur during a time span prior to reading the memory cell. In one implementation, such current compensation may be performed for each of one or more steps of an applied current staircase, as described in detail below.

Facts

Application: 13/913,714Filed 10 Jun 2013 · continuation
Priority: 15 Oct 2010
Published: US 2013/0272063 A117 Oct 2013
Granted: 16 Dec 2014
Term ends: 15 Oct 2030
Estimated · howhide
20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification10 codes

G11C 13/004
Auxiliary circuits: reading or sensing circuits or methods
G11C 11/5678
Using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency: using…
G11C 13/0004
Using resistive RAM [RRAM] elements: comprising amorphous/crystalline phase transition cells
G11C 13/0035
Auxiliary circuits: evaluating degradation, retention or wearout, e.g. by counting writing cycles

Family

Application12/905,754Parent of this continuation · filed 15 Oct 2010
US 2013/0272063 A1Pre-grant publication · published 17 Oct 2013
US 8,467,237 B2Parent of this continuation
US 2012/0092923 A1Published application
US 8,913,426 B2This patent

From the US filing history. Foreign family members aren’t listed.

Timeline

15 Oct 2010Priority claimedParent application 12/905,754
10 Jun 2013Application filedUS 13/913,714
17 Oct 2013PublishedUS 2013/0272063 A1
16 Dec 2014GrantedUS 8,913,426 B2
12 May 2016Assigned to U.S. Bank National Association, AS Collateral Agentsecurity interest
2 Jun 2016Assigned to Morgan Stanley Senior Funding, Inc., AS Collateral Agentpatent security agreement
8 Jun 2017Assigned to U.S. Bank National Association, AS Collateral Agentcorrective assignment to correct the replace erroneously filed patent #7358718 with the correct patent #7358178 previously recorded on reel 038669 frame 0001. assignor(s) hereby confirms the security interest.
13 Jul 2018Assigned to Jpmorgan Chase Bank, N.A., AS Collateral Agentsecurity interest
23 Aug 2018Assigned to Micron Technology, Inc.release of security interest
9 Oct 2019Assigned to Micron Technology, Inc.release of security interest
12 Nov 2019Assigned to Micron Technology, Inc., Micron Semiconductor Products, Inc.release of security interest
12 Oct 2026TodayWithin its term
15 Oct 2030Term endsEstimated