Phase change memory mask
AssigneeIntel Corporation
InventorDaniel J. Chu
Life of this patent
Estimating the term…
Abstract
Technology for writing data to a phase change memory array is disclosed. In an example, a method may include identifying mask logic for masking cells in the phase change memory array and routing the mask logic to the cells. The method may further include routing input data to the cells. Set and reset pulses for the cells may be selectively prevented or inhibited based on the mask logic.
Drawings
Claims23
A phase change memory, comprising:
- an array of phase change memory cells;
- and
- a mask receiver for individual cells in the array to receive a mask, identify existing data, identify input data and determine whether to inhibit a set pulse.
A method of writing data to a phase change memory array, comprising:
- identifying mask logic for masking cells in the phase change memory array;
- routing the mask logic to the cells;
- routing input data to the cells;
- and
- selectively preventing set and reset pulses for the cells based on the mask logic.
A data storage system, comprising:
- a processor;
- a power source;
- a phase change memory coupled to the processor and including an array of cells;
- a sequence controller to route a mask to the array of cells;
- and
- mask receivers at individual cells in the array of cells to receive the mask, identify existing data, identify input data and determine whether to inhibit a set pulse or a reset pulse to the cells.
Dependencies are inferred from the claim text.