Reducing source loading effect in spin torque transfer magnetoresistive random access memory (STT-MRAM)

#The present disclosure is generally directed to reducing a source loading effect in spin torque transfer magnetoresistive random access memory (STT-MRAM).

#Advances in non-volatile memory technology include resistance-based memory technologies, such as Magnetoresistive Random Access Memory (MRAM). MRAM technology is an emerging non-volatile memory technology that employs ferromagnetic-based Magnetic Tunnel Junctions (MTJs) as the basic memory elements. A commonly used array architecture for MRAMs is the one-transistor, one-MTJ (1T1MTJ) architecture. As the name suggests, each bit cell in this architecture consists of an MTJ connected in series with an n-channel metal-oxide-semiconductor (NMOS) access transistor. In order to leverage the increased density and area reduction advantages associated with scaling down NMOS technologies, it is desirable to use smaller transistors and lower operating voltages for the MRAM bit cell. However, while scaling down NMOS technology into the deep submicron regime yields area and density benefits, difficulties may arise in designing an 1T1MTJ architecture with stable operation, particularly with respect to a source loading effect.

#In a particular embodiment, a method is disclosed that includes determining a switching current ratio of a magnetic tunnel junction (MTJ) structure that enables stable operation of a memory cell. The memory cell includes the MTJ structure coupled to an access transistor. The method also includes modifying an offset magnetic field that is incident to a free layer of the MTJ structure. The modified offset magnetic field causes the MTJ structure to exhibit the switching current ratio. The offset magnetic field may result from magnetostatic couplings between the free layer and its adjacent layers in the MTJ structure.

#FIG. 1 is a block diagram of a particular illustrative embodiment of a memory device including a memory cell haying a programmed offset magnetic field;

#FIG. 2 is a diagram of a particular illustrative embodiment of memory cell having a programmed offset magnetic field;

#FIG. 3 is a diagram of a first illustrative embodiment of a magnetic tunnel junction (MTJ) structure haying a programmed offset magnetic field;

#Referring to FIG. 1, a diagram of a particular illustrative embodiment of a memory device including a memory cell having a programmed offset magnetic field is depicted and generally designated 100. The memory device 100 may include a memory array 102, such as spin torque transfer magnetoresistive random access memory (STT-MRAM) memory array. The memory array 102 includes a memory cell 116 having a programmed offset magnetic field. The memory array 102 may be coupled by bit lines 104 to a bit line logic circuit 106. The memory array 102 may be coupled by word lines 108 to a word line logic circuit 110. The memory array 102 may also be coupled to an amplifier 112.

#In a particular embodiment, the memory cell 116 having the programmed offset magnetic field includes a magnetic tunnel junction (NM) structure coupled to an access transistor in a 1T1MTJ configuration. As will be discussed with respect to FIGS. 2-8, the memory cell 116 may have one or more physical dimensions selected to program an offset magnetic field of the MTJ structure. The offset magnetic field is programmed to shift critical switching points of the MTJ to enable writing data values to the memory cell 116 when the access transistor is in a source loading operating state.

#FIG. 2 is a diagram of a particular illustrative embodiment of a memory cell having a programmed offset magnetic field. The memory cell 200 includes a substrate 202 having an access transistor 204 coupled to a MTJ structure 206 via a conductive path 208, such as one or more metal or polysilicon wires, contacts, or vias. In a particular embodiment, the memory cell 200 is the memory cell 116 of FIG. 1.