Writing to a memory cell
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsAllen Fan, Kuoyuan (Peter) Hsu
Life of this patent
Estimating the term…
Abstract
In a method, various operations are performed based on a voltage line coupled with a plurality of memory cells. Storage nodes of the plurality of memory cells are caused to change to a first logical value. Another first logical value is applied to a plurality of data lines. Each data line of the plurality of data lines carries data for each memory cell of the plurality of memory cells. A control line of the plurality of memory cells is activated. A first voltage value is applied to the voltage line. The first voltage value causes the another first logical value on the plurality of data lines to be transferred to the storage nodes of the plurality of memory cells.
Claims20
A method comprising:
- based on a voltage line coupled with a plurality of memory cells,
- causing storage nodes of the plurality of memory cells to have a predetermined logical value by turning off the plurality of memory cells;
- applying a set of logical values to a plurality of data lines, wherein each data line of the plurality of data lines carries data for each memory cell of the plurality of memory cells;
- activating a control line of the plurality of memory cells, wherein the control line is coupled with the plurality of memory cells;
- and
- applying a first voltage value to the voltage line sufficient to turn on the plurality of memory cells, wherein the first voltage value causes the set of logical values on the plurality of data lines to be transferred to the corresponding storage nodes of the plurality of memory cells.
A memory cell comprising:
- a first transistor of a first type;
- a second transistor of the first type;
- a first transistor of a second type different from the first type;
- a second transistor of the second type;
- a third transistor of the second type;
- and
- a fourth transistor of the second type,
- wherein
- the first transistor of the first type, the second transistor of the first type, the first transistor of the second type, and the second transistor of the second type are configured as a cross-coupled pair of inverters;
- the third transistor of the second type is configured as a first passgate transistor;
- the fourth transistor of the second type is configured as a second passgate transistor;
- a first terminal of the third transistor of the second type is configured as a first node, and is coupled with a first terminal of the second transistor of the first type;
- and
- the memory cell is configured such that a driving capability of the third transistor of the second type is configured to be the same as a driving capability of the second transistor of the first type.
A method comprising:
- based on a memory cell having a passgate transistor of a first type and a first transistor of a second type, wherein a first terminal of the passgate transistor is coupled with a first terminal of the first transistor, and serves as a first storage node of the memory cell, and wherein a size of the passgate transistor is configured to be equal to a size of the first transistor, performing the following operations
- applying a first voltage value to a second terminal of the first transistor to turn off the memory cell such that the first storage node has a predetermined logical value;
- applying a to-be-written logical value to a second terminal of the passgate transistor;
- activating a control line coupled with a second terminal of the passgate transistor;
- and
- applying a second voltage value to the second terminal of the first transistor to turn on the memory cell such that the first storage node has the to-be-written logical value from the second terminal of the passgate transistor, wherein the second voltage value is different from the first voltage value.
Dependencies are inferred from the claim text.