Random access memory controller having common column multiplexer and sense amplifier hardware

#The technology described herein relates generally to a memory controller and more particularly to a memory controller having common modules with common circuitry.

#Random access memory provides a form of computer data storage, where data or groups of data can be accessed in any order. Random access memory is often volatile memory, where stored data is lost when the memory is not powered. For example, dynamic random access memory must be periodically refreshed for data to be reliably stored. In contrast, static random access memory can retain data without refreshing, as long as the static random access memory remains powered.

#The description above is presented as a general overview of related art in this field and should not be construed as an admission that any of the information it contains constitutes prior art against the present patent application.

#FIG. 1 is a simplified block diagram depicting a random access memory controller in accordance with an embodiment of the disclosure.

#FIG. 2 is a block diagram depicting additional details of the random access memory controller embodiment of FIG. 1

#FIG. 3 is a block diagram showing an enlargement of the sense amplifier column multiplexer pair depicted in FIG. 2, including details of the common circuitry, in an embodiment.

#FIG. 1 is a simplified block diagram depicting a random access memory controller 102 in accordance with an embodiment of the disclosure. The random access memory controller 102 interfaces with a memory array 104 to facilitate reading data from the memory array 104 or writing data to the memory array 104. The memory array 104 could take a variety of forms. For example, the memory array 104 can be a component of a random access memory, such as a static random access memory, a non-volatile memory, an on-chip or off-chip cache memory, such as a level 1 (L1), level 2 (L2), or level 3 (L3) cache associated with a data processor, as well as other forms of memory. Cells of a memory array 104 are typically arranged into rows and columns, with one portion of data, such as a bit, being associated with each cell. The memory array 104 is accessible by columns, where all or a portion of data values in a column of the memory array 104 are outputted in series or in parallel in response to a data request. For example, when one or more data values from a sixth column 106 are requested to be read from or written to the memory array 104, all of the data values in the sixth column 106 are outputted or written to via one or more data lines 110 by the random access memory controller 102. In one embodiment, the random access memory controller 102 filters and combines data values received from the memory array 104 so that data is provided to a requesting application that meets the read data request.

#The random access memory controller 102 includes circuitry that is suited for reading from and writing to the memory array. In one embodiment, the random access memory controller 102 includes a column multiplexer 108. In a read operation, a command is received by the random access memory controller 102 to access data from one or more addresses of the memory array 104. The column multiplexer 108 receives data values from a column of the memory array 104 via the one or more data lines 110 of the memory array. In one example, eight bits of data of a requested column are accessed by the column multiplexer 108 via output data lines 110 associated with that column of data. In an example, the output data lines 110 are differential data lines, where the data lines 110 provide complementary high and low voltages in a pre-defined pattern to represent different bit values.

#In one embodiment, the column multiplexer 108, receives the data values and performs certain pre-processing on the data values to improve reliability of access. In one example, the column multiplexer 108 includes pre-charging circuitry, equalizing circuitry, and keeper circuitry for accessing, processing, and temporarily storing the data values for access by downstream circuitry in the data read process.