Semiconductor memory device and driving method thereof

A semiconductor memory device comprising:

• a first bit line;
• a second bit line;
• four or more word lines;
• a first sub bit line;
• a second sub bit line;
• a third sub bit line;
• a fourth sub bit line;
• a first transistor;
• a second transistor;
• a third transistor;
• a fourth transistor;
• a fifth transistor;
• a sixth transistor;
• a first inverter, wherein an output terminal of the first inverter is electrically connected to the second bit line through the first transistor;
• a second inverter, wherein an output terminal of the second inverter is electrically connected to the first bit line through the second transistor;
• a first memory block;
• a second memory block;
• a third memory block;
• and
• a fourth memory block,
• wherein the first memory block, the second memory block, the third memory block, and the forth memory block each include two or more memory cells,
• wherein the first memory block, the second memory block, the third memory block, and the fourth memory block are electrically connected to the first sub bit line, the second sub bit line, the third sub bit line, and the fourth sub bit line, respectively,
• wherein the first sub bit line is electrically connected to an input terminal of the first inverter through the third transistor,
• wherein the second sub bit line is electrically connected to the input terminal of the first inverter through the fourth transistor,
• wherein the third sub bit line is electrically connected to an input terminal of the second inverter through the fifth transistor, and
• wherein the forth sub bit line is electrically connected to the input terminal of the second inverter through the sixth transistor.

A semiconductor memory device comprising:

• a bit line;
• a sub bit line;
• two or more memory cells each including a transistor and a capacitor;
• a first transistor;
• a second transistor;
• a third transistor;
• a fourth transistor;
• a first inverter provided between the first transistor and the fourth transistor;
• and
• a second inverter provided between the second transistor and the third transistor and between the third transistor and the fourth transistor,
• wherein the sub bit line is electrically connected to the bit line through the third transistor and the first transistor, and
• wherein the first transistor and the second transistor are configured so that one of the first transistor and the second transistor is in an on state when the other of the first transistor and the second transistor is in an off state.