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AssigneeSK hynix Inc.
InventorJu Young Kim
Estimating the term…
A semiconductor apparatus may include a plurality of through-semiconductor chip lines which pass through a plurality of stacked semiconductor chips. An uppermost semiconductor chip among the plurality of stacked semiconductor chips is configured to transfer its internal information signal to an assigned corresponding through-semiconductor chip line, and at least one semiconductor chip other than the uppermost semiconductor chip is configured to logically combine respective internal information signals transferred through through-semiconductor chip lines and their internal information signals and sequentially transfer resultant signals to assigned corresponding through-semiconductor chip lines. The at least one semiconductor chip other than the uppermost semiconductor chip logically combines the internal information signals transferred through the through-semiconductor chip lines from adjoining semiconductor chips and its internal information signals.
A semiconductor apparatus including a plurality of through-semiconductor chip lines which pass through a plurality of stacked semiconductor chips,
A semiconductor apparatus including a plurality of through-semiconductor chip lines which pass through a plurality of stacked semiconductor chips, wherein an uppermost semiconductor chip among the plurality of stacked semiconductor chips is configured to transfer its internal information signal to an assigned corresponding through-semiconductor chip line, and remaining semiconductor chips are configured to logically combine respective internal information signals transferred through through-semiconductor chip lines and their internal information signals and sequentially transfer resultant signals to assigned corresponding through-semiconductor chip lines, the respective remaining semiconductor chips logically combining the internal information signals transferred through the through-semiconductor chip lines from adjoining semiconductor chips and their internal information signals,
Dependencies are inferred from the claim text.
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Management or control of the refreshing or charge-regeneration cycles: temperature related aspects of refresh operations
Management or control of the refreshing or charge-regeneration cycles: refresh operations over multiple banks or interleaving
Accessing single arrays: serial access; Scan testing
Accessing single arrays: scan chain
About 6 years of term left · ends 26 Oct 2032 (estimated)
The present application claims priority under 35 U.S.C. §119(a) to Korean Patent Application No. 10-2010-0119817, filed on, Nov. 29, 2010, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as if set forth in full.
1. Technical Field
Various embodiments of the present invention relates to a semiconductor system having a semiconductor apparatus comprising a plurality of stacked semiconductor chips and a controller. In particular, certain embodiments relate to a technology for outputting internal information signals of respective semiconductor chips.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.
FIG. 1 is a conceptual diagram of a semiconductor system in accordance with an embodiment of the present invention; and
FIG. 2 is a circuit diagram illustrating a detailed embodiment of the semiconductor apparatus shown in FIG. 1.
Reference will now be made in detail to the exemplary embodiments consistent with the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference characters will be used throughout the drawings to refer to the same or like parts.
For reference, since terms, symbols and signs that are used in drawings and in this detailed description to designate devices, blocks, and so on may be used for detailed units as the occasion demands, it is to be noted that the same terms, symbols and signs may not designate the same devices, blocks, and so on in an entire circuitry. Also, the logic signals of a circuit and binary data values are divided into a high level (H) or a low level (L) in correspondence to voltage levels and may be represented as ‘1’ and ‘0’. Furthermore, as the occasion demands, a high impedance state (a high-Z state) may be defined and described.
In order to achieve high degree of integration in a semiconductor memory apparatus and a semiconductor apparatus, various types of packages have been suggested. In particular, in a chip stack type in which a plurality of semiconductor chips are stacked to form one semiconductor apparatus, through-semiconductor chip lines may be used to commonly transfer signals across the plurality of semiconductor chips. Since semiconductor chips are usually manufactured from a single silicon wafer, the through-semiconductor chip lines are also called through-silicon vias (TSVs).